Abstract: A semiconductor structure includes an insulator, a semiconductor fin, a gate stack, a gate contact, a source/drain material, and a source/drain contact structure. The semiconductor fin protrudes from the insulator. The gate stack is disposed on the semiconductor fin and the insulator. The gate contact is disposed on and electrically connected to the gate stack. The source/drain material is disposed on the semiconductor fin. The source/drain contact structure is disposed on and electrically connected to the source/drain material. The semiconductor fin extends along a first direction, the gate stack extends along a second direction different from the first direction. An offset S in the second direction between the gate contact and the source/drain contact structure satisfies: 0<S?(W/2+D/2), wherein W is a width of the semiconductor fin, and D is a dimension of the gate contact.

Abstract: An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.

Abstract: An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.

Abstract: An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.

Abstract: A method for establishing an aging model of a device is provided. The device is measured to obtain degradation information of the device under an operating condition, wherein the device is a physical device. The degradation information is partitioned into a permanent degradation portion and an impermanent degradation portion. The impermanent degradation portion is differentiated by time to obtain a differential value. The aging model is obtained according to the differential value. When the differential value is greater than zero, a degradation of the device increases over time, and when the differential value is less than zero, the degradation of the device decreases over time.

Abstract: A method for establishing an aging model of a device is provided. The device is measured to obtain degradation information of the device under an operating condition, wherein the device is a physical device. The degradation information is partitioned into a permanent degradation portion and an impermanent degradation portion. The impermanent degradation portion is differentiated by time to obtain a differential value. The aging model is obtained according to the differential value. When the differential value is greater than zero, a degradation of the device increases over time, and when the differential value is less than zero, the degradation of the device decreases over time.

Abstract: A method of designing a circuit includes designing a first layout of the circuit based on a first plurality of corner variation values for an electrical characteristic of a corresponding plurality of back end of line (BEOL) features of the circuit. Based on the layout, a processor calculates a first delay attributable to the plurality of BEOL features and a second delay attributable to a plurality of front end of line (FEOL) devices of the circuit. If the first delay is greater than the second delay, a second layout of the circuit is designed based on a second plurality of corner variation values for the electrical characteristic of the corresponding plurality of BEOL features. Each corner variation value of the first plurality of corner variation values is obtained by multiplying a corresponding corner variation value of the second plurality of corner variation values by a corresponding scaling factor.

Abstract: A method includes receiving input information related to devices of an integrated circuit. A first simulation of the integrated circuit is performed over a first time period. Average temperature changes of the devices over the first time period are calculated. A second simulation of the integrated circuit is performed over a second time period using the average temperature changes of the devices. The first simulation and the second simulation are executed by a processor unit.

Abstract: An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.

Abstract: A method of designing a circuit includes designing a first layout of the circuit based on a first plurality of corner variation values for an electrical characteristic of a corresponding plurality of back end of line (BEOL) features of the circuit. Based on the layout, a processor calculates a first delay attributable to the plurality of BEOL features and a second delay attributable to a plurality of front end of line (FEOL) devices of the circuit. If the first delay is greater than the second delay, a second layout of the circuit is designed based on a second plurality of corner variation values for the electrical characteristic of the corresponding plurality of BEOL features. Each corner variation value of the first plurality of corner variation values is obtained by multiplying a corresponding corner variation value of the second plurality of corner variation values by a corresponding scaling factor.

Abstract: A method of generating a techfile corresponding to a predetermined fabrication process is disclosed. The method includes determining a typical value and a corner variation value usable to model an electrical characteristic of a layer of back end of line (BEOL) features to be fabricated by the predetermined fabrication process, based on measurement of one or more sample integrated circuit chips fabricated by the predetermined fabrication process. A reduced variation value is calculated based on the corner variation value and a scaling factor. The techfile is generated based on the typical value and the reduced variation value.

Abstract: A system and method for designing integrated circuits and predicting current mismatch in a metal oxide semiconductor (MOS) array. A first subset of cells in the MOS array is selected and current measured for each of these cells. Standard deviation of current for each cell in the first subset of cells is determined with respect to current of a reference cell. Standard deviation of local variation can be determined using the determined standard deviation of current for one or more cells in the first subset. Standard deviations of variation induced by, for example, poly density gradient effects, in the x and/or y direction of the array can then be determined and current mismatch for any cell in the array determined therefrom.

Abstract: A method of designing a circuit includes receiving a circuit design, and determining a temperature change of at least on back end of line (BEOL) element of the circuit design. The method further includes identifying at least one isothermal region within the circuit design; and determining, using a processor, a temperature increase of at least one front end of line (FEOL) device within the at least one isothermal region. The method further includes combining the temperature change of the at least one BEOL element with the temperature change of the at least one FEOL device, and comparing the combined temperature change with a threshold value.

Abstract: A method of generating a techfile corresponding to a predetermined fabrication process is disclosed. The method includes determining a typical value and a corner variation value usable to model an electrical characteristic of a layer of back end of line (BEOL) features to be fabricated by the predetermined fabrication process, based on measurement of one or more sample integrated circuit chips fabricated by the predetermined fabrication process. A reduced variation value is calculated based on the corner variation value and a scaling factor. The techfile is generated based on the typical value and the reduced variation value.

Abstract: In some embodiments, in a method, a layout of a circuit is received. A netlist with indicated pattern density (PD)-dependent mismatch elements associated with different PDs, respectively, is generated using the layout. A simulation on the netlist is performed such that when the PD-dependent mismatch elements are modeled in the simulation, corresponding model parameters of the PD-dependent mismatch elements are generated using variation distributions with different spreads.

Abstract: A method includes receiving input information related to devices of an integrated circuit. A first simulation of the integrated circuit is performed over a first time period. Average temperature changes of the devices over the first time period are calculated. A second simulation of the integrated circuit is performed over a second time period using the average temperature changes of the devices. The first simulation and the second simulation are executed by a processor unit.

Abstract: A method of designing a circuit includes receiving a circuit design, and determining a temperature change of at least on back end of line (BEOL) element of the circuit design. The method further includes identifying at least one isothermal region within the circuit design; and determining, using a processor, a temperature increase of at least one front end of line (FEOL) device within the at least one isothermal region. The method further includes combining the temperature change of the at least one BEOL element with the temperature change of the at least one FEOL device, and comparing the combined temperature change with a threshold value.

Abstract: In some embodiments, in a method, a layout of a circuit is received. A netlist with indicated pattern density (PD)-dependent mismatch elements associated with different PDs, respectively, is generated using the layout. A simulation on the netlist is performed such that when the PD-dependent mismatch elements are modeled in the simulation, corresponding model parameters of the PD-dependent mismatch elements are generated using variation distributions with different spreads.

Abstract: A system and method for designing integrated circuits and predicting current mismatch in a metal oxide semiconductor (MOS) array. A first subset of cells in the MOS array is selected and current measured for each of these cells. Standard deviation of current for each cell in the first subset of cells is determined with respect to current of a reference cell. Standard deviation of local variation can be determined using the determined standard deviation of current for one or more cells in the first subset. Standard deviations of variation induced by, for example, poly density gradient effects, in the x and/or y direction of the array can then be determined and current mismatch for any cell in the array determined therefrom.

Abstract: A system and method for designing integrated circuits and predicting current mismatch in a metal oxide semiconductor (MOS) array. A first subset of cells in the MOS array is selected and current measured for each of these cells. Standard deviation of current for each cell in the first subset of cells is determined with respect to current of a reference cell. Standard deviation of local variation can be determined using the determined standard deviation of current for one or more cells in the first subset. Standard deviations of variation induced by, for example, poly density gradient effects, in the x and/or y direction of the array can then be determined and current mismatch for any cell in the array determined therefrom.