Patents by Inventor Chung-Li Wang

Chung-Li Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11920055
    Abstract: A process for producing a barrier composition includes subjecting a siloxane compound having 1 to 3 amino groups and an aqueous solution including water and an alcohol to hydrolysis and first-stage condensation under required conditions, subjecting a first colloidal mixture obtained and an additional alcohol to second-stage condensation, subjecting a second colloidal mixture obtained, which has a particular solid content, to heating under required conditions, and subjecting a cured product obtained to aging under required conditions. A barrier composition produced by the process is also disclosed.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: March 5, 2024
    Assignee: NATIONAL TAIPEI UNIVERSITY OF TECHNOLOGY
    Inventors: Chung-Kuang Yang, Yi-Hsuan Lai, Sheng-Tung Huang, Kun-Li Wang
  • Patent number: 11115051
    Abstract: Systems and methods are provided for decoding a codeword encoded by a linear block code. A method may comprise performing a hard decision decoding on a codeword, determining which check nodes are satisfied and which check nodes are unsatisfied after the hard decision decoding, scheduling a check node processing order by moving at least one unsatisfied check node to be processed ahead of at least one satisfied check node and performing a soft decision decoding on the codeword according to the check node processing order.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: September 7, 2021
    Assignee: INNOGRIT TECHNOLOGIES CO., LTD.
    Inventors: Yuan-mao Chang, Jie Chen, Chung-Li Wang
  • Patent number: 10715182
    Abstract: Systems and methods are provided for decoding a codeword encoded by a linear block code. A method may comprise performing a hard decision decoding on a codeword, recording a number of flip(s) for each bit of the codeword, generating reliability information for each bit based on the number of flip(s) for each bit respectively, determining to switch to soft decision decoding according to a switching rule and performing a soft decision decoding on the codeword using the reliability information for each bit.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: July 14, 2020
    Assignee: Innogrit Technologies Co., Ltd.
    Inventors: Jie Chen, Chung-Li Wang, Zining Wu
  • Publication number: 20200082388
    Abstract: An authenticating server is coupled to a blockchain network is configured to: (1) receive a transaction application data from a user, wherein the transaction application data includes a wallet data containing a wallet address data and a user's signature data; (2) check whether an amount of a cryptocurrency corresponding to the wallet address data on the blockchain network is sufficient to perform the transaction; and (3) when the amount of the cryptocurrency corresponding to the wallet address data on the blockchain network is sufficient to perform the transaction, transmit a multi-signature wallet transaction data to the blockchain network for validating a blockchain operation, and send a confirmation data of the transaction associated with the transaction application data to an opposing party of the transaction. The multi-signature wallet transaction data includes the wallet address data, the user's signature data and a signature date of the authenticating server.
    Type: Application
    Filed: December 12, 2018
    Publication date: March 12, 2020
    Inventors: Chung-Li WANG, Chun-Wei HUANG, Haw YUAN, Chi-Liang CHENG, Hong-Bin YANG, Li-Zhong YEO, Yu-Chieh TSENG
  • Patent number: 10574274
    Abstract: Systems and methods are provided for decoding a codeword encoded by a linear block code. A method may comprise performing a first decoding on a codeword using a first decoder, determining a number of satisfied check nodes and a number of unsatisfied check nodes for a symbol value of the codeword for a decoding result of the first decoding, generating a soft log-likelihood ratio (LLR) for the symbol value based on the number of satisfied check nodes and the number of unsatisfied check nodes, and performing a second decoding using a second decoder with the soft LLR as an input to the second decoder.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: February 25, 2020
    Assignee: Nyquist Semiconductor Limited
    Inventors: Yuan-mao Chang, Jie Chen, Chung-Li Wang
  • Publication number: 20200059243
    Abstract: Systems and methods are provided for decoding a codeword encoded by a linear block code. A method may comprise performing a hard decision decoding on a codeword, determining which check nodes are satisfied and which check nodes are unsatisfied after the hard decision decoding, scheduling a check node processing order by moving at least one unsatisfied check node to be processed ahead of at least one satisfied check node and performing a soft decision decoding on the codeword according to the check node processing order.
    Type: Application
    Filed: October 25, 2019
    Publication date: February 20, 2020
    Inventors: Yuan-mao Chang, Jie Chen, Chung-Li Wang
  • Publication number: 20200036395
    Abstract: Systems and methods are provided for decoding a codeword encoded by a linear block code. A method may comprise performing a hard decision decoding on a codeword, recording a number of flip(s) for each bit of the codeword, generating reliability information for each bit based on the number of flip(s) for each bit respectively, determining to switch to soft decision decoding according to a switching rule and performing a soft decision decoding on the codeword using the reliability information for each bit.
    Type: Application
    Filed: July 27, 2018
    Publication date: January 30, 2020
    Inventors: Jie Chen, Chung-Li Wang, Zining Wu
  • Patent number: 10511326
    Abstract: Systems and methods are provided for decoding a codeword encoded by a linear block code. A method may comprise performing a soft decision decoding on a codeword, generating a hard decision for each bit of the codeword at an end of the soft decision decoding, generating a hard decision for each bit of the codeword at an end of the soft decision decoding, generating a reliability determination for each hard decision and performing a hard decision decoding using the hard decision for each bit and reliability determination for each hard decision.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: December 17, 2019
    Assignee: Nyquist Semiconductor Limited
    Inventors: Yuan-mao Chang, Jie Chen, Chung-Li Wang
  • Patent number: 10491244
    Abstract: Systems and methods are provided for decoding a codeword encoded by a linear block code. A method may comprise performing a hard decision decoding on a codeword, determining which check nodes are satisfied and which check nodes are unsatisfied after the hard decision decoding, scheduling a check node processing order by moving at least one unsatisfied check node to be processed ahead of at least one satisfied check node and performing a soft decision decoding on the codeword according to the check node processing order.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: November 26, 2019
    Assignee: Nyquist Semiconductor Limited
    Inventors: Yuan-mao Chang, Jie Chen, Chung-Li Wang
  • Publication number: 20190149169
    Abstract: Systems and methods are provided for decoding a codeword encoded by a linear block code. A method may comprise performing a hard decision decoding on a codeword, determining which check nodes are satisfied and which check nodes are unsatisfied after the hard decision decoding, scheduling a check node processing order by moving at least one unsatisfied check node to be processed ahead of at least one satisfied check node and performing a soft decision decoding on the codeword according to the check node processing order.
    Type: Application
    Filed: November 14, 2017
    Publication date: May 16, 2019
    Inventors: Yuan-mao Chang, Jie Chen, Chung-Li Wang
  • Publication number: 20190149168
    Abstract: Systems and methods are provided for decoding a codeword encoded by a linear block code. A method may comprise performing a soft decision decoding on a codeword, generating a hard decision for each bit of the codeword at an end of the soft decision decoding, generating a hard decision for each bit of the codeword at an end of the soft decision decoding, generating a reliability determination for each hard decision and performing a hard decision decoding using the hard decision for each bit and reliability determination for each hard decision.
    Type: Application
    Filed: November 14, 2017
    Publication date: May 16, 2019
    Inventors: Yuan-mao Chang, Jie Chen, Chung-Li Wang
  • Publication number: 20190103885
    Abstract: Systems and methods are provided for decoding a codeword encoded by a linear block code. A method may comprise performing a first decoding on a codeword using a first decoder, determining a number of satisfied check nodes and a number of unsatisfied check nodes for a symbol value of the codeword for a decoding result of the first decoding, generating a soft log-likelihood ratio (LLR) for the symbol value based on the number of satisfied check nodes and the number of unsatisfied check nodes, and performing a second decoding using a second decoder with the soft LLR as an input to the second decoder.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Yuan-mao Chang, Jie Chen, Chung-Li Wang
  • Patent number: 10141072
    Abstract: Memory systems may include a memory portion, and a controller suitable for receiving information data, generating first stage data, generating a first portion parity information, generating a second portion parity information based at least in part on the first portion parity information and the first stage data, and outputting the second portion parity information.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: November 27, 2018
    Assignee: SK Hynix Inc.
    Inventors: Wei-Hao Yuan, Chung-Li Wang, Johnson Yen
  • Patent number: 10135464
    Abstract: A method for decoding low-density parity check (LDPC) codes, includes computing an initial syndrome of an initial output, obtaining an initial number of unsatisfied checks based on the computed initial syndrome, and when the initial number of unsatisfied checks is greater than zero, computing a reliability value with a parity check, performing a bit flip operation, computing a subsequent syndrome of a subsequent output, and ending decoding when a number of unsatisfied checks obtained based on the computed subsequent syndrome is equal to zero.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: November 20, 2018
    Assignee: SK Hynix Inc.
    Inventors: Chung-Li Wang, Lingqi Zeng, Yi-Min Lin
  • Patent number: 9996285
    Abstract: Memory systems may include a memory storage including at least a first stripe and a second stripe, the first stripe including data pages corresponding to the first stripe and a first parity page suitable for storing a first XOR parity, and the second stripe including data pages corresponding to the second stripe and a second parity page suitable for storing a second XOR parity, the data pages and parity pages being stored over a plurality of memory dies, wherein each memory die includes a number of planes; and a controller suitable for cyclically interleaving the data pages corresponding to the first stripe and the data pages corresponding to the second stripe.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: June 12, 2018
    Assignee: SK Hynix Inc.
    Inventors: Jingyu Kang, Chung-Li Wang, Cai Wang, Yibo Zhang
  • Publication number: 20180129430
    Abstract: Memory systems may include a memory storage including at least a first stripe and a second stripe, the first stripe including data pages corresponding to the first stripe and a first parity page suitable for storing a first XOR parity, and the second stripe including data pages corresponding to the second stripe and a second parity page suitable for storing a second XOR parity, the data pages and parity pages being stored over a plurality of memory dies, wherein each memory die includes a number of planes; and a controller suitable for cyclically interleaving the data pages corresponding to the first stripe and the data pages corresponding to the second stripe.
    Type: Application
    Filed: November 8, 2016
    Publication date: May 10, 2018
    Inventors: Jingyu Kang, Chung-Li Wang, Cai Wang, Yibo Zhang
  • Patent number: 9906240
    Abstract: A decoder includes a syndrome generator for receiving a codeword and generating at least two syndromes based on the codeword, an error location polynomial generator for generating an error-location polynomial based on the syndromes, an error location determiner for determining at least one error location based on the error-location polynomial, and an error corrector for correcting the codeword based on the one error location. The error location polynomial generator includes a logic for receiving the syndromes and generating a combination of the syndromes as a combination of coefficients of the error-location polynomial, and a key equation solver for generating the error-location polynomial based on the combination of the coefficients and finding at least one root of the error-location polynomial. The error location determiner determines the error location based on a combination of the root and one of the syndromes.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: February 27, 2018
    Assignee: SK Hynix Inc.
    Inventors: Yi-Min Lin, Aman Bhatia, Naveen Kumar, Chung-Li Wang, Lingqi Zeng
  • Patent number: 9866241
    Abstract: Techniques are described for an adaptive low density parity check (LDPC) decoder. The techniques include receiving a first set of values corresponding to a first low density parity check codeword and noise, performing a first plurality of iterations of an iterative decoding algorithm using a first set of decoding parameters to decode the received first set of values, comparing a metric with a first threshold, and upon determining that the metric is larger than the threshold: selecting a second set of decoding parameters for the iterative LDPC decoder and performing a second plurality of iterations of the iterative LDPC decoding algorithm using the second set of decoding parameters to decode the received first set of values and generate a first set of decoded bits.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: January 9, 2018
    Assignee: SK Hynix Inc.
    Inventors: Johnson Yen, Abhiram Prabhakar, Chung-Li Wang
  • Patent number: 9710326
    Abstract: A first physical location is read to obtain read data. Error correction decoding is performed on the read data to obtain error-corrected data where the error-corrected data includes first error-corrected metadata. Error correction encoding is performed on a first random sequence combined with a second random sequence, concatenated with second metadata. Error correction encoding is also performed on a sequence of zeros concatenated with the first error-corrected metadata to obtain second encoded data. The error-corrected data, the first encoded data, and the second encoded data are summed to obtain migrated data, which is stored at a second physical location.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: July 18, 2017
    Assignee: SK Hynix Inc.
    Inventors: Fan Zhang, Chung-Li Wang, Chun Hok Ho
  • Publication number: 20170093428
    Abstract: Techniques are described for an adaptive low density parity check (LDPC) decoder. The techniques include receiving a first set of values corresponding to a first low density parity check codeword and noise, performing a first plurality of iterations of an iterative decoding algorithm using a first set of decoding parameters to decode the received first set of values, comparing a metric with a first threshold, and upon determining that the metric is larger than the threshold: selecting a second set of decoding parameters for the iterative LDPC decoder and performing a second plurality of iterations of the iterative LDPC decoding algorithm using the second set of decoding parameters to decode the received first set of values and generate a first set of decoded bits.
    Type: Application
    Filed: March 17, 2016
    Publication date: March 30, 2017
    Inventors: Johnson Yen, Abhiram Prabhakar, Chung-Li Wang