Abstract: A layered LDPC decoder architecture includes a single MUX and a single shifter element for processing an optimized LDPC parity check matrix. The optimized LDPC parity check matrix may be a K×L sub-matrix having zero elements, non-zero elements defined by a circulant matrix or zero matrices, and identity matrixes.

Abstract: A LDPC decoder includes a processor for targeted symbol flipping of suspicious bits in a LDPC codeword with unsatisfied checks. All combinations of check indices and variable indices are compiled and correlated into a pool of targeted symbol flipping candidates and returned along with symbol indices to a process that uses such symbol indices to identify symbols to flip in order to break a trapping set.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for mis-correction detection and correction in a data processing system.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding including utilization of different scaling values on a portion by portion basis during the data decoding.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a combination data decoder circuit. The combination data decoder circuit includes: a non-binary data decoder circuit and a binary data decoder circuit.

Abstract: A data processing system is disclosed including a data decoder circuit, an error handling circuit and a syndrome checker circuit. The data decoder circuit is operable to apply a data decode algorithm to a decoder input to yield a decoded output, and to calculate a syndrome indicating an error level for the decoded output. The error handling circuit is operable to determine whether any errors in the decoded output involve user data bits. The syndrome checker circuit is operable to trigger the error handling circuit based at least in part on the syndrome.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding.

Abstract: An apparatus for layered low density parity check decoding includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to calculate perceived data values based on check node to variable node messages. The check node processor includes an intermediate message generator circuit operable to generate intermediate check node messages, a shift register based memory operable to store the intermediate check node messages, and at least one check node to variable node message generator circuit operable to generate the check node to variable node messages based on the intermediate check node messages from the shift register based memory.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes: a data detector circuit, a data decoder circuit, and a power usage control circuit. The data detector circuit is operable to apply a data detection algorithm to a data input to yield a detected output. The data decoder circuit is operable to apply a data decode algorithm to a data set derived from the detected output to yield a decoded output. The power usage control circuit is operable to force a defined number of global iterations applied to the data input by the data detector circuit and the data decoder circuit regardless of convergence of the data decode algorithm.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for multi-stage encoding for concatenated low density parity check codes.

Abstract: Systems, methods, devices, circuits for a min-sum based hybrid non-binary low density parity check decoder.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding including utilization of different scaling values on a portion by portion basis during the data decoding.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding including skipping one or more codeword blocks in the data decoding process.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding.

Abstract: A LE hard decision memory comprises a global mapping element to interleave L values from a first and second circulant and store the interleaved values in a first memory element. A low-density parity-check decoder then processes the circulants from the first memory element and stores output in a second memory element. The LE hard decision memory does not include any mux-demux elements.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, data processing systems are disclosed that include: a data decoder circuit, a decoder log, a mis-correction detection circuit, and a controller circuit.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, data processing systems are disclosed that include a data decoding circuit having a data decoder circuit, an element modification circuit, an element modification log, and a mis-correction detection circuit.