Patents by Inventor Chung-Lin Wu

Chung-Lin Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110066818
    Abstract: A storage device, a memory controller, and a data protection method are provided. The method includes when receiving a read command sent by a host, adopting a corresponding output flow rate limit to determine an operation that is executed on read data corresponding to the read command by the host according to location information included in the read command or a type of a transmission interface between the host and the storage device. The method also includes executing an interference procedure by the storage device to prevent the read data from being copied to the host or slow down the speed of copying the read data to the host when identifying that the operation is a copy operation.
    Type: Application
    Filed: June 24, 2010
    Publication date: March 17, 2011
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Hsiang-Hsiung Yu, Chung-Lin Wu, Yi-Hsiang Huang, Yu-Chung Shen
  • Publication number: 20110059580
    Abstract: An exemplary semiconductor die package of the invention has a metal-oxide substrate disposed between a first surface of a semiconductor die and a heat-sinking component, with a conductive die clip or one or more electrical interconnect traces disposed between the metal-oxide substrate and the first surface of the semiconductor die. The heat-sinking component may comprise a heat sink, or an adaptor plate to which a heat sink may be coupled. The conductive die clip or electrical trace(s) provides electrical connection(s) to the first surface of the semiconductor die, while the metal-oxide substrate electrically insulates the die from the heat-sinking component, and provides a path of high thermal conductivity between the die and the heat-sinking component. The second surface of the semiconductor die may be left free to connect to a circuit board, or a leadframe or interconnect substrate may be attached to it.
    Type: Application
    Filed: September 15, 2010
    Publication date: March 10, 2011
    Inventors: Oseob Jeon, Chung-Lin Wu, Eddy Tjhia, Bigildis C. Dosdos
  • Patent number: 7845214
    Abstract: This invention relates to a device and method for optical nanoindentation measurement, according to which respective measurement results are obtained by having an indenter tip apply load to a fixed portion of a thin film, having an indenter tip apply load to a non-fixed portion of a thin film, and having a vibrating component transmit the dynamic properties of the vibration to the thin film. By combining the above measurement results in calculations, the Young's modulus, the Poisson's ratio, and the density of the thin film can be obtained.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: December 7, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Jiong-Shiun Hsu, Hui-Ching Lu, Chung-Lin Wu, Sheng-Jui Chen
  • Patent number: 7821124
    Abstract: Semiconductor die packages and methods of making them are disclosed. An exemplary package comprises a leadframe having a source lead and a gate lead, and a semiconductor die coupled to the source and gate leads at a first surface of the leadframe. The source lead has a protruding region at a second surface of the leadframe. A molding material is disposed around the semiconductor die, the gate lead, and the source lead such that a surface of the die and a surface of the protruding region are left exposed by the molding material. An exemplary method comprises obtaining the semiconductor die and leadframe, and forming a molding material around at least a portion of the leadframe and die such that a surface of the protruding region is exposed through the molding material.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: October 26, 2010
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Rajeev Joshi, Chung-Lin Wu
  • Publication number: 20100258925
    Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.
    Type: Application
    Filed: June 25, 2010
    Publication date: October 14, 2010
    Inventors: Oseob Jeon, Yoonhwa Choi, Boon Huan Gooi, Maria Cristina B. Estacio, David Chong, Tan Teik Keng, Shibaek Nam, Rajeev Joshi, Chung-Lin Wu, Venkat Iyer, Lay Yeap Lim, Byoung-Ok Lee
  • Patent number: 7800219
    Abstract: An exemplary semiconductor die package of the invention has a metal-oxide substrate disposed between a first surface of a semiconductor die and a heat-sinking component, with a conductive die clip or one or more electrical interconnect traces disposed between the metal-oxide substrate and the first surface of the semiconductor die. The heat-sinking component may comprise a heat sink, or an adaptor plate to which a heat sink may be coupled. The conductive die clip or electrical trace(s) provides electrical connection(s) to the first surface of the semiconductor die, while the metal-oxide substrate electrically insulates the die from the heat-sinking component, and provides a path of high thermal conductivity between the die and the heat-sinking component. The second surface of the semiconductor die may be left free to connect to a circuit board, or a leadframe or interconnect substrate may be attached to it.
    Type: Grant
    Filed: January 2, 2008
    Date of Patent: September 21, 2010
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Oseob Jeon, Chung-Lin Wu, Eddy Tjhia, Bigildis C. Dosdos
  • Patent number: 7772681
    Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.
    Type: Grant
    Filed: June 19, 2006
    Date of Patent: August 10, 2010
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Rajeev Joshi, Chung-Lin Wu, Venkat Iyer
  • Publication number: 20100148325
    Abstract: Disclosed are semiconductor dice with backside trenches filled with elastic conductive material. The trenches reduce the on-state resistances of the devices incorporated on the dice. The elastic conductive material provides a conductive path to the backsides of the die with little induced stress on the semiconductor die caused by thermal cycling. Also disclosed are packages using the dice, and methods of making the dice.
    Type: Application
    Filed: December 12, 2008
    Publication date: June 17, 2010
    Inventors: Michael D. Gruenhagen, Suku Kim, James J. Murphy, Eddy Tjhia, Chung-Lin Wu, Mark Larsen, Douglas E. Dolan
  • Publication number: 20100123225
    Abstract: Disclosed are semiconductor die structures that enable a die having a vertical power device to be packaged in a wafer-level chip scale package where the current-conducting terminals are present at one surface of the die, and where the device has very low on-state resistance. In an exemplary embodiment, a trench and an aperture are formed in a backside of a die, with the aperture contacting a conductive region at the top surface of the die. A conductive layer and/or a conductive body may be disposed on the trench and aperture to electrically couple the backside current-conducting electrode of the device to the conductive region. Also disclosed are packages and systems using a die with a die structure according to the invention, and methods of making dice with a die structure according to the invention.
    Type: Application
    Filed: November 20, 2008
    Publication date: May 20, 2010
    Inventors: Michael D. Gruenhagen, Suku Kim, James J. Murphy, Ihsiu Ho, Eddy Tjhia, Chung-Lin Wu, Mark Larsen, Rohit Dikshit
  • Publication number: 20100117231
    Abstract: A wafer level chip scale package (WLCSP) includes a semiconductor device with a plurality of solder bump pads, patterned passivation regions above each of the solder bump pads, a patterned under bump metallization (UBM) region on each of the solder bump pads and the passivation regions, a polyimide region over a portion of the UBM regions and the passivation regions, solder bumps formed on each of the UBM regions.
    Type: Application
    Filed: January 20, 2010
    Publication date: May 13, 2010
    Inventors: Dennis Lang, Sonbol Vaziri, James Kent Naylor, Eric Woolsey, Chung-Lin Wu, Mike Gruenhagen, Neill Thornton
  • Patent number: 7635635
    Abstract: A method of bonding a semiconductor substrate to a metal substrate is disclosed. In some embodiments the method includes forming a semiconductor device in a semiconductor substrate, the semiconductor device comprising a first surface. The method further includes obtaining a metal substrate. The metal substrate is bonded to the first surface of the semiconductor device, wherein at least a portion of the metal substrate forms an electrical terminal for the semiconductor device.
    Type: Grant
    Filed: April 6, 2006
    Date of Patent: December 22, 2009
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Hamza Yilmaz, Qi Wang, Minhua Li, Chung-Lin Wu
  • Publication number: 20090261461
    Abstract: Semiconductor packages comprising a plurality of lead fingers containing a lead intrusion at the edge of the lead fingers are described. The semiconductor packages comprise an integrated circuit chip that is connected to a die pad and is electrically connected to multiple lead fingers. One or more of the lead fingers may have a lead intrusion disposed on the external exposed lower surface of the lead finger. The lead intrusion may have a height that is about ? to about ½ the height of a lead finger, a width that is about ? to about 1/2 the width of a lead finger, and a depth that is about ¼ to about ¾ the length of the externally exposed lower surface of a lead finger. The lead intrusion increases the area on the lead finger that contacts a bond material, such as solder, and therefore increase the strength of the joint between the semiconductor package and an external surface to which the lead finger is connected (i.e., a PCB).
    Type: Application
    Filed: April 16, 2008
    Publication date: October 22, 2009
    Inventors: Steven Sapp, Chung-Lin Wu, Maria Christina B. Estacio, Bigildis Dosdos, Hamza Yilmaz
  • Publication number: 20090165537
    Abstract: This invention relates to a device and method for optical nanoindentation measurement, according to which respective measurement results are obtained by having an indenter tip apply load to a fixed portion of a thin film, having an indenter tip apply load to a non-fixed portion of a thin film, and having a vibrating component transmit the dynamic properties of the vibration to the thin film. By combining the above measurement results in calculations, the Young's modulus, the Poisson's ratio, and the density of the thin film can be obtained.
    Type: Application
    Filed: August 28, 2008
    Publication date: July 2, 2009
    Applicant: Industrial Technology Research Institute
    Inventors: Jiong-Shiun Hsu, Hui-Ching Lu, Chung-Lin Wu, Sheng-Jui Chen
  • Publication number: 20090166850
    Abstract: An exemplary semiconductor die package of the invention has a metal-oxide substrate disposed between a first surface of a semiconductor die and a heat-sinking component, with a conductive die clip or one or more electrical interconnect traces disposed between the metal-oxide substrate and the first surface of the semiconductor die. The heat-sinking component may comprise a heat sink, or an adaptor plate to which a heat sink may be coupled. The conductive die clip or electrical trace(s) provides electrical connection(s) to the first surface of the semiconductor die, while the metal-oxide substrate electrically insulates the die from the heat-sinking component, and provides a path of high thermal conductivity between the die and the heat-sinking component. The second surface of the semiconductor die may be left free to connect to a circuit board, or a leadframe or interconnect substrate may be attached to it.
    Type: Application
    Filed: January 2, 2008
    Publication date: July 2, 2009
    Inventors: Oseob Jeon, Chung-Lin Wu, Eddy Tjhia, Bigildis C. Dosdos
  • Patent number: 7525179
    Abstract: A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die including a first surface and a second surface, and a leadframe structure having a die attach region and a plurality of leads extending away from the die attach region. The die attach region includes one or more apertures. A molding material is around at least portions of the die attach region of the leadframe structure and the semiconductor die. The molding material is also within the one or more apertures.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: April 28, 2009
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Rajeev Joshi, Chung-Lin Wu
  • Publication number: 20090072362
    Abstract: A semiconductor package includes a semiconductor device 30 and a molded upper heat sink 10. The heat sink has an interior surface 16 that faces the semiconductor device and an exterior surface 15 that is at least partially exposed to the ambient environment of the packaged device. An annular planar base 11 surrounds a raised or protruding central region 12. That region is supported above the plane of the base 11 by four sloped walls 13.1-13.4. The walls slope at an acute angle with respect to the planar annular base and incline toward the center of the upper heat sink 10. Around the outer perimeter of the annular base 11 are four support arms 18.1-18.4. The support arms are disposed at an obtuse angle with respect to the interior surface 16 of the planar annular base 11.
    Type: Application
    Filed: July 10, 2008
    Publication date: March 19, 2009
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Chung-Lin Wu, Rajeev D. Joshi
  • Patent number: 7468548
    Abstract: A semiconductor package includes a semiconductor device 30 and a molded upper heat sink 10. The heat sink has an interior surface 16 that faces the semiconductor device and an exterior surface 15 that is at least partially exposed to the ambient environment of the packaged device. An annular planar base 11 surrounds a raised or protruding central region 12. That region is supported above the plane of the base 11 by four sloped walls 13.1-13.4. The walls slope at an acute angle with respect to the planar annular base and incline toward the center of the upper heat sink 10. Around the outer perimeter of the annular base 11 are four support arms 18.1-18.4. The support arms are disposed at an obtuse angle with respect to the interior surface 16 of the planar annular base 11.
    Type: Grant
    Filed: December 9, 2005
    Date of Patent: December 23, 2008
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Chung-Lin Wu, Rajeev D. Joshi
  • Publication number: 20080105957
    Abstract: Embodiments of the invention are directed to semiconductor die packages. One embodiment of the invention is directed to a semiconductor die package including, (a) a semiconductor die including a first surface and a second surface, (b) a source lead structure including protruding region having a major surface, the source lead structure being coupled to the first surface, (c) a gate lead structure being coupled to the first surface, and (d) a molding material around the source lead structure and the semiconductor die, where the molding material exposes the second surface of the semiconductor die and the major surface of the source lead structure.
    Type: Application
    Filed: December 20, 2007
    Publication date: May 8, 2008
    Inventors: Rajeev Joshi, Chung-Lin Wu
  • Publication number: 20080054461
    Abstract: A wafer level chip scale package (WLCSP) includes a packaged semiconductor device with a plurality of solder bump pads, patterned passivation regions above each of the solder bump pads, a patterned under bump metallization (UBM) region on each of the solder bump pads and the passivation regions, a polyimide region over a portion of the UBM regions and the passivation regions, solder bumps formed on each of the UBM regions, and encapsulation material surrounding the semiconductor die except for at least a portion of each of the solder bumps.
    Type: Application
    Filed: August 30, 2007
    Publication date: March 6, 2008
    Inventors: Dennis Lang, Sonbol Vaziri, James Naylor, Eric Woolsey, Chung-Lin Wu, Mike Gruenhagen, Neill Thornton
  • Patent number: 7335532
    Abstract: A multichip module package uses bond wire with plastic resin on one side of a lead frame to package an integrated circuit and flip chip techniques to attach one or more mosfets to the other side of the lead frame. The assembled multichip module 30 has an integrated circuit controller 14 on a central die pad. Wire bonds 16 extend from contact areas on the integrated circuit to outer leads 2.6 of the lead frame 10. On the opposite, lower side of the central die pad, the sources and gates of the mosfets 24, 26 are bump or stud attached to the half etched regions of the lead frame. The drains 36 of the mosfets and the ball contacts 22.1 on the outer leads are soldered to a printed circuit board.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: February 26, 2008
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Jonathan A. Noquil, Seung Yong Choi, Rajeev Joshi, Chung-Lin Wu