Patents by Inventor Chung Lin

Chung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250105019
    Abstract: A method is provided. The method includes: receiving a semiconductor structure having a first material and a second material; performing a first etch on the first material for a first duration under a first etching chemistry; and performing a second etch on the second material for a second duration under a second etching chemistry, wherein the first material includes a first incubation time and the second material includes a second incubation time greater than the first incubation time under the first etching chemistry. The first material includes a third incubation time and the second material includes a fourth incubation time less than the third incubation time under the second etching chemistry.
    Type: Application
    Filed: December 10, 2024
    Publication date: March 27, 2025
    Inventors: HAN-YU LIN, LI-TE LIN, TZE-CHUNG LIN, FANG-WEI LEE, YI-LUN CHEN, JUNG-HAO CHANG, YI-CHEN LO, FO-JU LIN, KENICHI SANO, PINYEN LIN
  • Publication number: 20250101484
    Abstract: The present disclosure includes an improved method of making a protein. The steps and conditions were described and carried out with significantly improved protein yield, thereby reducing manufacturing cost.
    Type: Application
    Filed: September 12, 2024
    Publication date: March 27, 2025
    Applicant: PharmaEssentia Corporation
    Inventors: Ko-Chung Lin, Yu-Kuei Tsai, Ming-Pin Hsu
  • Publication number: 20250107234
    Abstract: A display device has a display area and a peripheral area, and includes an array substrate. The array substrate includes M number of pixel unit columns disposed in the display area and a first dummy electrode disposed in the peripheral area, where M is a positive integer greater than or equal to 2. The M number of pixel unit columns include a first pixel unit column to an Mth pixel unit column arranged in sequence. Each of the M number of pixel unit columns includes a plurality of pixel units arranged in sequence. The first dummy electrode is located on one side of the first pixel unit column. During a frame period, the first pixel unit column receives the first pixel signal, and the first dummy electrode receives the first dummy signal. The polarity of the first pixel signal is different from that of the first dummy signal.
    Type: Application
    Filed: July 1, 2024
    Publication date: March 27, 2025
    Inventors: Chung-Lin CHANG, Hsuan-Chen LIU, Yu-Cheng LIN, Chen-Hao SU
  • Patent number: 12261540
    Abstract: A dual mode charge control method includes steps of: detecting an input voltage of the resonance tank, a resonance current of the resonance tank, an output current of the load, and an output voltage of the load; performing a single-band charge control when determining a light-load condition or a no-load condition of the load according to the output current; compensating the output voltage to generate an upper threshold voltage in the single-band charge control, and acquiring a resonance voltage by calculating the resonance current by a resettable integrator; comparing the resonance voltage and the upper threshold voltage to generate a first control signal; generating a second control signal complementary to the first control signal by a pulse-width modulation duplicator; providing the first control signal and the second control signal to respectively control a first power switch and a second power switch of the resonance circuit.
    Type: Grant
    Filed: January 19, 2023
    Date of Patent: March 25, 2025
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Bo-Ruei Peng, Chang-Chung Lin, Yu-Jen Lin, Chia-Hsiong Huang
  • Patent number: 12253574
    Abstract: Current sharing in a power system having multiple PSUs comprises generating and supplying a first power and a second power to a load, and sensing a remote voltage value received by the load based on an accumulation of the first and second powers. The method further comprises determining, by the first PSU, local voltage and current values of the first power, a real impedance value of the first PSU based on the remote voltage value and the local voltage and current values of the first power, and a virtual impedance value of the first PSU based on the real impedance value of the first PSU and a reference impedance value. The method further comprises controlling generation of the first power by the first PSU based on the virtual impedance value of the first PSU.
    Type: Grant
    Filed: December 29, 2022
    Date of Patent: March 18, 2025
    Assignee: Advanced Energy Industries, Inc.
    Inventors: Chin-Feng Huang, Ping-Yang Lai, Sin-You Lin, Li-Chung Lin
  • Publication number: 20250089331
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a stack structure over a substrate, and the stack structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked. The method includes forming a dummy gate electrode over the first semiconductor layers and the second semiconductor layers, and forming a gate spacer layer adjacent to the dummy gate electrode. The method includes removing the second semiconductor layers to form a recess between two adjacent first semiconductor layers, and forming a dummy dielectric layer in the recess after the dummy gate electrode is formed. The dummy dielectric layer is between two adjacent first semiconductor layers. The method includes replacing the dummy gate electrode and the dummy dielectric layer with a gate structure.
    Type: Application
    Filed: November 25, 2024
    Publication date: March 13, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tze-Chung LIN, Han-Yu LIN, Li-Te LIN, Pinyen LIN
  • Publication number: 20250072164
    Abstract: A method for forming an indium gallium nitride quantum well structure is disclosed. The method includes forming a gallium nitride microdisk on a substrate, with the gallium nitride microdisk having an inverted pyramid form and an end face; and forming multiple quantum well layers on the end face, with each quantum well layer including an indium gallium nitride quantum well and a barrier layer. The indium gallium nitride quantum well is grown at a growth temperature adjusted using a trend equation within a temperature range of 480° C. to 810° C.
    Type: Application
    Filed: September 26, 2023
    Publication date: February 27, 2025
    Inventors: I-KAI LO, CHENG-DA TSAI, YU-CHUNG LIN, YING-CHIEH WANG, MING-CHI CHOU, TING-CHANG CHANG
  • Publication number: 20250071299
    Abstract: Encoding using media compression and processing for machine-learning-based quality metrics includes generating encoded frame data by encoding a current frame from an input video using a neural-network-based video quality model, which includes identifying optimal encoding parameters for encoding a current block, wherein the optimal encoding parameters minimize a rate-distortion optimization cost function, which includes using a gradient value for the current block obtained from a neural-network-based video quality model generated gradient map obtained from the neural-network-based video quality model for the current frame, obtaining a restoration filtered reconstructed frame by restoration filtering a reconstructed frame, obtained by decoding the encoded frame data, using the neural-network-based video quality model generated gradient map obtained for the reconstructed frame.
    Type: Application
    Filed: August 24, 2023
    Publication date: February 27, 2025
    Inventors: Yao-Chung Lin, Jingning Han, Yilin Wang, Yeping Su
  • Patent number: 12235136
    Abstract: A control method and a controller related to electromagnetic tracking are provided. In the method, a working position is determined, and the working position is the position at which a magnetic field sensor is located relative to a magnetic field emitter; an electrical characteristic of the magnetic field emitter or the magnetic field sensor is adjusted to a target characteristic corresponding to the working position. In this way, the positioning accuracy may be improved.
    Type: Grant
    Filed: December 6, 2022
    Date of Patent: February 25, 2025
    Assignee: Metal Industries Research & Development Centre
    Inventors: Zong-Hsin Liu, Po-Chi Hu, I-Chiao Tsai, Chih-Chung Lin
  • Patent number: 12224210
    Abstract: A semiconductor device includes a substrate, a semiconductor fin protruding from the substrate, an isolation layer disposed above the substrate, a dielectric fin with a bottom portion embedded in the isolation layer, and a gate structure over top and sidewall surfaces of the semiconductor fin and the dielectric fin. The semiconductor fin has a first sidewall and a second sidewall facing away from the first sidewall. The isolation layer includes a first portion disposed on the first sidewall of the semiconductor fin and a second portion disposed on the second sidewall of the semiconductor fin. A top portion of the dielectric fin includes an air pocket with a top opening sealed by the gate structure.
    Type: Grant
    Filed: May 8, 2023
    Date of Patent: February 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Han-Yu Lin, Yi-Ruei Jhan, Fang-Wei Lee, Tze-Chung Lin, Chao-Hsien Huang, Li-Te Lin, Pinyen Lin, Akira Mineji
  • Patent number: 12225709
    Abstract: A manufacturing method of a semiconductor device includes forming an opening in a substrate, implanting a dopant in the substrate from a sidewall of the opening such that a doping region is formed in the substrate at the sidewall of the opening, filling a dielectric material in the opening to form a first dielectric structure after implanting the dopant in the substrate from the sidewall of the opening, and forming a passing word line in the dielectric structure.
    Type: Grant
    Filed: February 21, 2024
    Date of Patent: February 11, 2025
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chung-Lin Huang
  • Patent number: 12225717
    Abstract: A semiconductor device includes a substrate, a passing word line in the substrate, and a dielectric structure surrounding the passing word line. The dielectric structure has an enlargement portion at a bottom of the dielectric structure, and a maximum width of the enlargement portion of the dielectric structure is wider than a width of a top of the dielectric structure.
    Type: Grant
    Filed: September 20, 2023
    Date of Patent: February 11, 2025
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chung-Lin Huang
  • Publication number: 20250041975
    Abstract: A laser slicing apparatus, in which a laser module provides a laser beam, and a light splitting element of a focusing lens set splits the laser beam into a plurality of focused laser beams to form a plurality of induce lines having first laser modified cracks in a modified layer at a predetermined depth inside a substrate. A rotating module rotates the light splitting element with an angle, and the light splitting element converts the focused laser beams according to this angle to form a plurality of modified groups between the induce lines. Each modified group includes a plurality of modified lines having second laser modified cracks, and the first laser modified cracks and the second laser modified cracks are connected to each other to form a continuous laser modified crack in the modified layer at the predetermined depth inside the substrate, thereby speeding up the laser slicing production.
    Type: Application
    Filed: September 11, 2023
    Publication date: February 6, 2025
    Applicant: Industrial Technology Research Institute
    Inventors: Jyun-Jhih WANG, Chun-Ming CHEN, Yu-Chung LIN, Pin-Hao HU, Chien-Jung HUANG
  • Patent number: 12219749
    Abstract: A semiconductor device structure and method for manufacturing the same are provided. The method includes: providing a substrate; forming a first word line and a second word line extending along a first direction; forming a dielectric material conformally on a first sidewall of the first word line and on a second sidewall of the second word line, wherein the second sidewall of the second word line faces the first sidewall of the first word line; forming a semiconductor material on a sidewall of the dielectric material; and patterning the dielectric material and the semiconductor material to form a gate dielectric structure and a channel layer between the first word line and the second word line.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: February 4, 2025
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Szu-Yao Chang, Chung-Lin Huang
  • Patent number: 12217961
    Abstract: A method for manufacturing a semiconductor device includes: forming a patterned hard mask on a patterned structure disposed on a substrate, such that a hard mask portion of the patterned hard mask is disposed on a fin portion of the patterned structure; and laterally trimming the hard mask portion by a lateral etching process. The lateral etching process includes a radical etching process and a chemical etching process. Alternatively, the lateral etching process includes a radical etching process, a plasma etching process, or a combination thereof, and a cleaning process.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Chien Kuang, Tze-Chung Lin, Li-Te Lin
  • Publication number: 20250037425
    Abstract: A method for diagnosing a reason of a malfunction is provided. The method includes: receiving a signal to be diagnosed; decomposing the signal to be diagnosed into a plurality of sub-signals; transforming each of the plurality of sub-signals into a corresponding grayscale image; and inputting the corresponding grayscale images to a neural network model, and outputting a malfunction reason classification result through the neural network model. Accordingly, the method can be used for diagnosing the reason of the malfunction and solves the problem of incapable of diagnosing the reason of the malfunction. In addition, a device and a computer-readable recording medium for diagnosing the reason of the malfunction are also provided.
    Type: Application
    Filed: October 6, 2023
    Publication date: January 30, 2025
    Inventors: WEI-JYUN TU, YU-YEN CHEN, CHIEN-CHUNG LIN
  • Patent number: D1065614
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: March 4, 2025
    Inventor: Chi-Chung Lin
  • Patent number: D1065630
    Type: Grant
    Filed: November 6, 2024
    Date of Patent: March 4, 2025
    Inventor: Chi-Chung Lin
  • Patent number: D1065631
    Type: Grant
    Filed: November 6, 2024
    Date of Patent: March 4, 2025
    Inventor: Chi-Chung Lin
  • Patent number: D1065632
    Type: Grant
    Filed: November 6, 2024
    Date of Patent: March 4, 2025
    Inventor: Chi-Chung Lin