Patents by Inventor Chung Lin

Chung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240088227
    Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The method includes forming first and second nanostructured channel regions in first and second nanostructured layers, respectively, and forming first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The forming the first and second GAA structures includes selectively forming an Al-based n-type work function metal layer and a Si-based capping layer on the first nanostructured channel regions, depositing a bi-layer of Al-free p-type work function metal layers on the first and second nanostructured channel regions, depositing a fluorine blocking layer on the bi-layer of Al-free p-type work function layers, and depositing a gate metal fill layer on the fluorine blocking layer.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang CHENG, Chun-I WU, Huang-Lin CHAO
  • Publication number: 20240087989
    Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Josh LIN, Chung-Jen HUANG, Yun-Chi WU, Tsung-Yu YANG
  • Publication number: 20240090232
    Abstract: A ferroelectric memory cell (FeRAM) is disclosed that includes an active device (e.g., a transistor) and a passive device (e.g., a ferroelectric capacitor) integrated in a substrate. The transistor and its gate contacts are formed on a front side of the substrate. A carrier wafer can be bonded to the active device to allow the active device to be inverted so that the passive device and associated contacts can be electrically coupled from a back side of the substrate.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang CHENG, Huang-Lin CHAO
  • Patent number: 11929258
    Abstract: An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue
  • Publication number: 20240081154
    Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.
    Type: Application
    Filed: November 8, 2023
    Publication date: March 7, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Tai-Cheng Hou, Fu-Yu Tsai, Bin-Siang Tsai, Da-Jun Lin, Chau-Chung Hou, Wei-Xin Gao
  • Publication number: 20240078679
    Abstract: Methods, systems, and apparatuses for image segmentation are provided. For example, a computing device may obtain an image, and may apply a process to the image to generate input image feature data and input image segmentation data. Further, the computing device may obtain reference image feature data and reference image classification data for a plurality of reference images. The computing device may generate reference image segmentation data based on the reference image feature data, the reference image classification data, and the input image feature data. The computing device may further blend the input image segmentation data and the reference image segmentation data to generate blended image segmentation data. The computing device may store the blended image segmentation data within a data repository. In some examples, the computing device provides the blended image segmentation data for display.
    Type: Application
    Filed: September 1, 2022
    Publication date: March 7, 2024
    Inventors: Chung-Chi TSAI, Shubhankar Mangesh BORSE, Meng-Lin WU, Venkata Ravi Kiran DAYANA, Fatih Murat PORIKLI, An CHEN
  • Patent number: 11921530
    Abstract: A power supply system includes an output terminal, a power supply control chip, a power supply switch and a detection device. The power supply control chip is configured to adjust the amount of an input power providing to an electronic device by the power supply device. The power supply switch is configured to control the connection between the power supply device and the power supply control chip. The detection device is configured to detect whether the power supply control chip operates normally. When the power supply control chip operates abnormally, the detection device controls the connection between the power supply device and the power supply control chip through the power supply switch for restarting the power supply control chip. The power supply control chip, the power supply switch and the detection device are disposed in an enclosed space.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: March 5, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Shih-Chung Wang, Cheng-Yu Shu, Wei-Chieh Lin
  • Publication number: 20240069609
    Abstract: In one or more embodiments, an information handling system may include: at least one processor; a memory medium, communicatively coupled to the at least one processor, that stores an operating system and at least one application executable by the at least one processor; a chassis; an information handling system card port communicatively coupled to the at least one processor; a support device fastened to the chassis; and an expansion card coupled to the information handling system card port and fastened to the support device. In one or more embodiments, the support device may include an opening that permits air to pass through. In one or more embodiments, the support device may include a cover configured to obscure airflow through the opening of the support device. For example, the cover may be configured to unroll to obscure airflow through the opening of the support device.
    Type: Application
    Filed: August 23, 2022
    Publication date: February 29, 2024
    Inventors: Yu-Ming Kuo, Chung-An Lin, Qinghong He, Derric Christopher Hobbs
  • Patent number: 11916127
    Abstract: Various embodiments of the present disclosure are directed towards a memory device including a first bottom electrode layer over a substrate. A ferroelectric switching layer is disposed over the first bottom electrode layer. A first top electrode layer is disposed over the ferroelectric switching layer. A second bottom electrode layer is disposed between the first bottom electrode layer and the ferroelectric switching layer. The second bottom electrode layer is less susceptible to oxidation than the first bottom electrode layer.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi Yang Wei, Bi-Shen Lee, Hsin-Yu Lai, Hai-Dang Trinh, Hsing-Lien Lin, Hsun-Chung Kuang
  • Publication number: 20240057322
    Abstract: A semiconductor structure includes a semiconductor substrate; a spacer located in a trench of the semiconductor substrate, wherein the spacer includes two trench nitride layers and an empty gap sandwiched between the two trench nitride layers; a first nitride layer disposed to seal an exposed opening of the empty gap between the two trench nitride layers; a second nitride layer over the first nitride layer, wherein the second nitride layer has a higher density than the first nitride layer; and a third nitride layer having a first portion over the second nitride layer and a second portion disposed on sidewalls of the two trench nitride layers.
    Type: Application
    Filed: October 23, 2023
    Publication date: February 15, 2024
    Inventors: Yu-Ying LIN, Chung-Lin HUANG
  • Publication number: 20240038959
    Abstract: A display includes micro LEDs connected to a color conversion layer and driver ICs connected to the micro LEDs via an electrically connecting layer. Each micro LEDs includes an N pad and a P pad. The micro LEDs emit light of a same color, and the color conversion layer converts the light into various colors. The electrically connecting layer includes elongated negative electrodes connected to the N pads and elongated positive electrodes connected to the P pads. Each driver IC includes a first group of bonding pads on a face, a second group of bonding pads on an opposite face, and conductors for connecting the first group of bonding pads to the second group of bonding pads. Each bonding pad in the first group is connected to an elongated negative or positive electrode. The circuit board is connected to the second group of bonding pads of each driver IC.
    Type: Application
    Filed: October 13, 2023
    Publication date: February 1, 2024
    Inventors: CHIH-MENG WU, CHIEN-KUO TIEN, CHUN-CHUNG LIN
  • Patent number: 11889597
    Abstract: A light fixture of a light system is configured to be dimmable using a dimming signal that is either a direct-current (DC) dimming signal or an alternating-current (AC) dimming signal. For example, a 0-10 volt DC dimming signal could be used, or a 120 volt AC dimming signal could be used. A dimming controller in the light fixture is configured to receive both a DC and an AC dimming signals and adjust a brightness and/or color of a light based on the dimming signal.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: January 30, 2024
    Assignee: Tivoli, Inc.
    Inventors: Lien-Chung Lin, Bey Shing Jang
  • Publication number: 20240027858
    Abstract: A signal control method suitable for a touch screen is provided. The signal control method comprises: switching a plurality of scan lines to an enabling voltage level sequentially in a display stage; turning on a plurality of switches sequentially to transmit a plurality of display data to a plurality of data lines when a first scan line of the plurality of scan lines is in an enabled voltage level, wherein a first switch of the plurality of switches is coupled to a first data line of the plurality of data lines, and the first data line corresponds to one of a plurality of dummy lines in a vertical direction, when the first scan line is in the enabled voltage level, the first switch is turned on after other switches are turned on; and setting the plurality of dummy lines to a touch voltage in a touch stage.
    Type: Application
    Filed: November 23, 2022
    Publication date: January 25, 2024
    Inventors: Shih-Hsi CHANG, Yu-Hsin TING, Chung-Lin FU, I-Fang CHEN, Wei-Chun HSU, Nan-Ying LIN
  • Patent number: 11878424
    Abstract: A robot interference checking motion planning technique using point sets. The technique uses CAD models of robot arms and obstacles and converts the CAD models to 3D point sets. The 3D point set coordinates are updated at each time step based on robot and obstacle motion. The 3D points are then converted to 3D grid space indices indicating space occupied by any point on any part. The 3D grid space indices are converted to 1D indices and the 1D indices are stored as sets per object and per time step. Interference checking is performed by computing an intersection of the 1D index sets for a given time step. Swept volumes are created by computing a union of the 1D index sets across multiple time steps. The 1D indices are converted back to 3D coordinates to define the 3D shapes of the swept volumes and the 3D locations of any interferences.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: January 23, 2024
    Assignee: FANUC CORPORATION
    Inventors: Hsien-Chung Lin, Yongxiang Fan, Tetsuaki Kato
  • Patent number: 11881037
    Abstract: An automatically detecting method for time-varying text region of interest is disclosed. The automatically detecting method is adapted to an image processing unit of an information retrieval system, to detect a time-varying text region of interest having specific characters or character set as unit on an operation screen of a manufacturing machine, a processing machine or other equipment; furthermore, the automatically detecting method can be performed based on presence or absence of the historical screen data, and union of the detected region proposals for the time-varying text region of interest, to obtain an automatically labeled and selected time-varying text region of interest. According to the automatically detecting method, the user only needs to confirm whether the required data are labeled and selected, so it is more convenient for the user to setting data, and greatly helpful to reduce the setting time and correctly detect the required information.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: January 23, 2024
    Assignee: ADLINK TECHNOLOGY INC.
    Inventors: Chien-Chung Lin, Wei-Jyun Tu, Yu-Yen Chen
  • Publication number: 20240021453
    Abstract: A method includes transferring a tool monitoring device over a load port of a tool. A bottom of the tool monitoring device has a plurality of holes, and the load port comprises a plurality of pins at a top surface of the load port. The tool monitoring device is placed on the top surface of the load port. The pins at the top surface of the load port are plugged into the holes of the tool monitoring device. Heights of the pins are sensed to identifying a type of the load port after the tool monitoring device is placed on the top surface of the load port. An environment around the load port is monitored by using the tool monitoring device.
    Type: Application
    Filed: July 28, 2023
    Publication date: January 18, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hom-Chung LIN, Chi-Ying CHANG, Jih-Churng TWU, Chin-Yun CHEN, Yi-Ting CHANG, Feng-Yu CHEN
  • Patent number: 11872704
    Abstract: A method and system for dynamic collision avoidance motion planning for industrial robots. An obstacle avoidance motion optimization routine receives a planned path and obstacle detection data as inputs, and computes a commanded robot path which avoids any detected obstacles. Robot joint motions to follow the tool center point path are used by a robot controller to command robot motion. The planning and optimization calculations are performed in a feedback loop which is decoupled from the controller feedback loop which computes robot commands based on actual robot position. The two feedback loops perform planning, command and control calculations in real time, including responding to dynamic obstacles which may be present in the robot workspace. The optimization calculations include a safety function which efficiently incorporates both relative position and relative velocity of the obstacles with respect to the robot.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: January 16, 2024
    Assignee: FANUC CORPORATION
    Inventors: Hsien-Chung Lin, Chiara Talignani Landi, Chi-Keng Tsai, Tetsuaki Kato
  • Patent number: D1011242
    Type: Grant
    Filed: October 26, 2023
    Date of Patent: January 16, 2024
    Inventor: Chi-Chung Lin
  • Patent number: D1011243
    Type: Grant
    Filed: October 26, 2023
    Date of Patent: January 16, 2024
    Inventor: Chi-Chung Lin
  • Patent number: D1017085
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: March 5, 2024
    Inventor: Chi-Chung Lin