Patents by Inventor Chung Liu

Chung Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11979980
    Abstract: A first and second patterned circuit layer are formed on a first surface and a second surface of a base material. A first adhesive layer is formed on the first patterned circuit layer. A portion of the first surface is exposed by the first patterned circuit layer. The metal reflection layer covers the first insulation layer and a reflectance thereof is greater than or equal to 85%, there is no conductive material between the first patterned circuit layer and the metal reflection layer, and the first adhesive layer is disposed between the first patterned circuit layer and the first insulation layer. A transparent adhesive layer and a protection layer are formed on the metal reflection layer. The transparent adhesive layer is disposed between the metal reflection layer and the protection layer. The protection layer comprises a transparent polymer. The light transmittance is greater than or equal to 80%.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: May 7, 2024
    Assignee: UNIFLEX Technology Inc.
    Inventors: Cheng-I Tu, Ying-Hsing Chen, Meng-Huan Chia, Hsin-Ching Su, Yi-Chun Liu, Cheng-Chung Lai, Yuan-Chih Lee
  • Publication number: 20240145378
    Abstract: An interconnect structure on a semiconductor die includes: a lower conductive layer; an upper conductive layer disposed above the lower conductive layer; and a VIA disposed between the lower conductive layer and the upper conductive layer. The VIA includes: a primary interconnect structure and a sacrificial stress barrier ring disposed around the primary interconnect structure and separated a distance from the primary interconnect structure. A fabrication method for the interconnect structure includes: forming a dielectric layer over a lower conductive layer; patterning photoresist (PR) layer over the dielectric layer to define a location for a plurality of VIA trenches, wherein the patterning includes patterning the PR layer to provide a center opening for the VIA trenches that is surrounded by a ring opening for the VIA trenches, wherein the center opening and the ring opening are spaced apart.
    Type: Application
    Filed: February 7, 2023
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Ting Liu, Chen-Chiu Huang, Dian-Hau Chen, Hung-Chao Kao, Hsiang-Ku Shen, Wen-Chiung Tu, Li Chung Yu, Yu-Chung Lai
  • Publication number: 20240144717
    Abstract: Disclosed are systems, apparatuses, processes, and computer-readable media to capture images. A method of processing image data includes determining a first region of interest (ROI) in an image. The first ROI is associated with a first object. The method can include determining one or more image characteristics of the first ROI. The method can further include determining whether to perform an upsampling process on image data in the first ROI based on the one or more image characteristics of the first ROI.
    Type: Application
    Filed: October 26, 2022
    Publication date: May 2, 2024
    Inventors: Wen-Chun FENG, Kai LIU, Su-Chin CHIU, Chung-Yan CHIH, Yu-Ren LAI
  • Publication number: 20240145630
    Abstract: A light-emitting device includes a substrate and an epitaxial structure. The epitaxial structure includes a first semiconductor layer, an active layer, and a second semiconductor layer which are disposed on the upper surface of the substrate in such order. The substrate has a substrate edge region surrounding and exposed from the epitaxial structure. The substrate edge region includes a first substrate edge region and a second substrate edge region which is more proximate to the epitaxial structure than the first substrate edge region. The first substrate edge region has a first uneven toothed surface or an even flat surface. The second substrate edge regions are formed with second uneven toothed surfaces which have a height greater than a height of the first even toothed surface, or the even flat surface.
    Type: Application
    Filed: October 31, 2023
    Publication date: May 2, 2024
    Inventors: Minyou HE, Xiaoliang LIU, Qing WANG, Ling-Yuan HONG, Chung-Ying CHANG
  • Patent number: 11973302
    Abstract: The present disclosure provides a method for aligning a master oscillator power amplifier (MOPA) system. The method includes ramping up a pumping power input into a laser amplifier chain of the MOPA system until the pumping power input reaches an operational pumping power input level; adjusting a seed laser power output of a seed laser of the MOPA system until the seed laser power output is at a first level below an operational seed laser power output level; and performing a first optical alignment process to the MOPA system while the pumping power input is at the operational pumping power input level, the seed laser power output is at the first level, and the MOPA system reaches a steady operational thermal state.
    Type: Grant
    Filed: February 20, 2023
    Date of Patent: April 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Lin Louis Chang, Henry Tong Yee Shian, Alan Tu, Han-Lung Chang, Tzung-Chi Fu, Bo-Tsun Liu, Li-Jui Chen, Po-Chung Cheng
  • Publication number: 20240135661
    Abstract: A extended reality communication system, methods, apparatus, and computer program product are disclosed. The communication system provides for remote real-time communication between a proctor and an operator, where the operator is performing tasks on a local work object, such as a patient. The system incorporates a combination of haptic, virtual keyboard, VR, XR, and audio inputs to provide communication of instructions between the proctor and the operator that are projected as a holographic image in a field of view on the patient. The system includes a proctor station and an operator station communicatively coupled with one or more servers.
    Type: Application
    Filed: October 23, 2023
    Publication date: April 25, 2024
    Inventors: Kyeong Baek Kim, Joon Chung, William H. Chapman, JR., Jafer Mujtaba Kamoonpuri, Beomseok Gwak, Adam Yongsuk Choe, Mohsen Rostami, Han Yu Liu, Pratik Pradhan, Joshua Dongwoo Choe
  • Publication number: 20240136444
    Abstract: A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.
    Type: Application
    Filed: December 22, 2023
    Publication date: April 25, 2024
    Inventors: Yu-Chu Lin, Chi-Chung Jen, Wen-Chih Chiang, Yi-Ling Liu, Huai-Jen Tung, Keng-Ying Liao
  • Publication number: 20240128231
    Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are presented. In embodiments the methods of manufacturing include depositing a first bonding layer on a first substrate, wherein the first substrate comprises a semiconductor substrate and a metallization layer. The first bonding layer and the semiconductor substrate are patterned to form first openings. A second substrate is bonded to the first substrate. After the bonding the second substrate, the second substrate is patterned to form second openings, at least one of the second openings exposing at least one of the first openings. After the patterning the second substrate, a third substrate is bonded to the second substrate, and after the bonding the third substrate, the third substrate is patterned to form third openings, at least one of the third openings exposing at least one of the second openings.
    Type: Application
    Filed: January 4, 2023
    Publication date: April 18, 2024
    Inventors: Fu Wei Liu, Pei-Wei Lee, Yun-Chung Wu, Bo-Yu Chiu, Szu-Hsien Lee, Mirng-Ji Lii
  • Publication number: 20240118592
    Abstract: Provided is a multi-functional mount for a webcam for installing the webcam on a computer display, and the webcam set on the mount is movable in a horizontal direction to an appropriate distance beyond the display and then rotated 90°, so that a camera lens of the webcam can be vertically oriented downward to capture an image on a table. The mount further includes a counterweight block, which is rotatable to adjust for obtaining the best position to balance the two ends of the mount and prevent the mount from tipping over the computer display. The mount can also be placed directly on a table with a combination of a plurality of base body bodies.
    Type: Application
    Filed: December 27, 2022
    Publication date: April 11, 2024
    Applicant: MAGIC CONTROL TECHNOLOGY CORPORATION
    Inventor: Pei-Chung LIU
  • Publication number: 20240120295
    Abstract: A semiconductor chip and a manufacturing method thereof are provided. The semiconductor chip includes: an array of pillar structures, disposed on a front surface of the semiconductor chip, and respectively including a ground pillar and multiple working pillars laterally spaced apart from and substantially parallel with a line portion of the ground pillar; and dummy pillar structures, disposed on the front surface of the semiconductor chip and laterally surrounding the pillar structures. Active devices formed inside the semiconductor chip are electrically connected to the working pillar. The ground pillars of the pillar structures and the dummy pillar structures are electrically connected to form a current pathway on the front surface of the semiconductor chip.
    Type: Application
    Filed: January 30, 2023
    Publication date: April 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Hsien Lee, Yun-Chung Wu, Pei-Wei Lee, Fu Wei Liu, Jhao-Yi Wang
  • Publication number: 20240110961
    Abstract: A signal transmission mechanism includes a first cable carrying arm, a second cable carrying arm and a pivoting module. The first connecting portion and the second connecting portion are connected through the pivoting module so that the first cable carrying arm and the second cable carrying arm can be rotated with respect to each other. The first cable carrying arm is configured to carry a first cable and the second cable carrying arm is configured to carry a second cable. The first cable and the second cable are electrically connected through the pivoting module. A signal is transmitted from the first cable through the pivoting module to the second cable. The first cable and the second cable are not deformed when the first cable carrying arm and the second cable carrying arm are rotated with respect to each other.
    Type: Application
    Filed: September 26, 2023
    Publication date: April 4, 2024
    Inventor: Rong-Chung Liu
  • Publication number: 20240113259
    Abstract: A light-emitting device includes a semiconductor epitaxial structure including a first semiconductor layer, an active layer, and a second semiconductor layer, and having holes; a first insulation layer disposed on the semiconductor epitaxial structure and having first and second grooves; a first pad electrically connected to the first semiconductor layer through the first grooves; and a second pad electrically connected to the second semiconductor layer through the second grooves. A projection of the first pad does not overlap projections of the holes. A projection of the second pad does not overlap the projections of the holes. The first pad includes a first pad connection portion and first pad extension portions; the second pad includes a second pad connection portion and second pad extension portions. Projections of the second grooves fall between projections of the first and second pad extension portions. Two other aspects of the light-emitting device are also provided.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 4, 2024
    Inventors: Xiushan ZHU, Qi JING, Yan LI, Xiaoliang LIU, Zhilong LU, Chunhsien LEE, Chi-Ming TSAI, Juchin TU, Chung-Ying CHANG
  • Patent number: 11946135
    Abstract: Processing methods for forming iridium-containing films at low temperatures are described. The methods comprise exposing a substrate to iridium hexafluoride and a reactant to form iridium metal or iridium silicide films. Methods for enhancing selectivity and tuning the silicon content of some films are also described.
    Type: Grant
    Filed: March 27, 2023
    Date of Patent: April 2, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Feng Q. Liu, Hua Chung, Schubert Chu, Mei Chang, Jeffrey W. Anthis, David Thompson
  • Patent number: 11948702
    Abstract: A radiation source apparatus includes a vessel, a laser source, a collector, a horizontal obscuration bar, and a reflective mirror. The vessel has an exit aperture. The laser source is configured to emit a laser beam to excite a target material to form a plasma. The collector is disposed in the vessel and configured to collect a radiation emitted by the plasma and to reflect the collected radiation to the exit aperture of the vessel. The horizontal obscuration bar extends from a sidewall of the vessel at least to a position between the laser source and the exit aperture of the vessel. The reflective mirror is in the vessel and connected to the horizontal obscuration bar.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Chung Tu, Sheng-Kang Yu, Shang-Chieh Chien, Li-Jui Chen, Heng-Hsin Liu
  • Publication number: 20240096834
    Abstract: A method is provided. The method includes determining a first bump map indicative of a first set of positions of bumps. The method includes determining, based upon the first bump map, a first plurality of bump densities associated with a plurality of regions of the first bump map. The method includes smoothing the first plurality of bump densities to determine a second plurality of bump densities associated with the plurality of regions of the first bump map. The method includes determining, based upon the second plurality of bump densities, a second bump map indicative of the first set of positions of the bumps and a set of sizes of the bumps.
    Type: Application
    Filed: March 27, 2023
    Publication date: March 21, 2024
    Inventors: Shih Hsuan HSU, Chan-Chung CHENG, Chun-Chen LIU, Cheng-Hung CHEN, Peng-Ren CHEN, Wen-Hao CHENG, Jong-l MOU
  • Patent number: 11935894
    Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.
    Type: Grant
    Filed: November 4, 2022
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-yuan Chang, Chun-Chen Chen, Po-Hsiang Huang, Lee-Chung Lu, Chung-Te Lin, Jerry Chang Jui Kao, Sheng-Hsiung Chen, Chin-Chou Liu
  • Patent number: 11937370
    Abstract: A base material is provided. A first patterned circuit layer and a second patterned circuit layer are formed on a first surface and a second surface of the base material. A first insulation layer and a metal reflection layer are provided on the first patterned circuit layer and a portion of the first surface exposed by the first patterned circuit layer, wherein the metal reflection layer covers the first insulation layer, and a reflectance of the metal reflection layer is substantially greater than or equal to 85%, there is no conductive material between the first patterned circuit layer and the metal reflection layer. A first ink layer is formed on the first insulation layer before the metal reflection layer is formed.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: March 19, 2024
    Assignee: UNIFLEX Technology Inc.
    Inventors: Cheng-I Tu, Ying-Hsing Chen, Meng-Huan Chia, Hsin-Ching Su, Yi-Chun Liu, Cheng-Chung Lai, Yuan-Chih Lee
  • Publication number: 20240087879
    Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.
    Type: Application
    Filed: November 14, 2023
    Publication date: March 14, 2024
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20240088327
    Abstract: A light emitting device includes a light-emitting laminate and an insulating reflective structure. The insulating reflective structure includes n pairs of dielectric layers stacked on the light-emitting laminate. Each of the n pairs of dielectric layers includes a first material layer and a second material layer. The first material layer has a first refractive index, and the second material layer has a second refractive index that is greater than the first refractive index of the first material layer. For each pair of dielectric layers among m1 pairs of dielectric layers out of the n pairs of dielectric layers, the first material layer has an optical thickness that is greater than that of the second material layer, where 0.5n?m1?n, and n and m1 are natural numbers greater than 0.
    Type: Application
    Filed: November 15, 2023
    Publication date: March 14, 2024
    Inventors: Shiwei LIU, Jin XU, Baojun SHI, Shuijie WANG, Ke LIU, Chung-ying CHANG
  • Publication number: 20240088154
    Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed directly on an upper surface of the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Alexander Kalnitsky, Kong-Beng Thei, Ming Chyi Liu, Shih-Chung Hsiao, Jhih-Bin Chen