Patents by Inventor Chung Peng

Chung Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12288740
    Abstract: According to various examples, a device is described. The device may include a first package substrate. The device may also include a first mold layer with a first thickness. The device may also include a second mold layer with a second thickness proximal to the first mold layer. The second thickness may be larger than the first thickness. The first mold layer may include a plurality of first interconnects coupled to the first package substrate. The second mold layer may include a plurality of second interconnects configured to couple the first package substrate to a printed circuit board.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: April 29, 2025
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Chia Chuan Wu, Jackson Chung Peng Kong, Kooi Chi Ooi
  • Patent number: 12256487
    Abstract: The present disclosure is directed to a hybrid dielectric interconnect stack for a printed circuit board having a first dielectric layer with a first dielectric constant and a first dielectric loss tangent positioned over an intermediate layer, which includes a first dielectric sublayer with a first sublayer dielectric constant and a first sublayer dielectric loss tangent, an embedded conductive layer, and a second dielectric sublayer with a second sublayer dielectric constant and a second sublayer dielectric loss tangent, in which the embedded conductive layer is positioned between the first and second dielectric sublayers, and a second dielectric layer with a second dielectric constant and a second dielectric loss tangent, in which the intermediate layer is positioned between the first and second dielectric layers.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: March 18, 2025
    Assignee: Intel Corporation
    Inventors: Jackson Chung Peng Kong, Bok Eng Cheah, Jenny Shio Yin Ong, Seok Ling Lim, Chin Lee Kuan, Tin Poay Chuah
  • Publication number: 20250087542
    Abstract: The present disclosure is directed to an improved stiffener that has a body that has extension members positioned proximally to the corners of a semiconductor package substrate, and the extension members have bottom extension surfaces that extend beyond a periphery of a bottom surface of the semiconductor package substrate, and the bottom extension surfaces and the bottom surface of the semiconductor package substrate are co-planar. The present disclosure is also directed to a method for forming the improved stiffener with the extension members for a semiconductor package.
    Type: Application
    Filed: September 13, 2023
    Publication date: March 13, 2025
    Inventors: Man Chun OOH, Wei Chung LEE, Yean Ling SOON, Kor Oon LEE, Jackson Chung Peng KONG, Azniza ABD AZIZ, Piyush BHATT
  • Patent number: 12218064
    Abstract: Disclosed embodiments include silicon interconnect bridges that are in a molded frame, where the molded frame includes passive devices and the silicon interconnect bridge includes through-silicon vias that couple to a redistribution layer on both the silicon interconnect bridge and the molded frame.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: February 4, 2025
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Jenny Shio Yin Ong, Seok Ling Lim, Jackson Chung Peng Kong, Kooi Chi Ooi
  • Patent number: 12206419
    Abstract: A delay-locked loop (DLL) circuit includes a low pass filter coupled to a phase detector, and a digitally controlled delay line (DCDL) coupled to the low pass filter. The DCDL includes an input terminal, an output terminal coupled to an input terminal of the phase detector, and stages that propagate a signal along a first path from the input terminal to a selectable return stage and along a second path from the return stage to the output terminal. Each stage includes first and second inverters that selectively propagate the signal along the first and second paths, a third inverter that selectively propagates the signal from the first path to the second path, and either fourth and fifth inverters that selectively propagate the signal along the first and second paths, or a sixth inverter that selectively propagates the signal from the first path to the second path.
    Type: Grant
    Filed: December 1, 2023
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Peng Hsieh, Chih-Chiang Chang, Yung-Chow Peng
  • Patent number: 12191281
    Abstract: The present disclosure is directed to semiconductor packages, and methods for making them, which includes a substrate with a top surface and a bottom surface, a substrate recess in the bottom surface of the substrate, a first device positioned over the top surface of the substrate, which has the first device at least partially overlapping the substrate recess, a mold material in the substrate recess, which has the mold material overlapping the bottom surface of the substrate adjacent to the substrate recess, a second device positioned in the substrate recess, and a plurality of interconnect vias in the substrate, which has at least one of the plurality interconnect vias coupled to the first and second devices to provide a direct signal connection therebetween that minimizes signal latency.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: January 7, 2025
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Yang Liang Poh, Seok Ling Lim, Jenny Shio Yin Ong, Jackson Chung Peng Kong
  • Publication number: 20250001622
    Abstract: An apparatus for automated maintenance, adapted for maintaining an airtight equipment comprises airtight equipment including a casing, which forms an accommodation space and is adapted to accommodate an equipment component in the accommodation space. The apparatus for automated maintenance includes an automated maintenance machine, adapted to store and transport the equipment component, an enclosure, connected to the automated maintenance machine, the enclosure forming an enclosure space and selectively connected to the airtight equipment via an enclosure opening such that the enclosure space is in communication with the accommodation space and forms airtightness. A robotic arm, disposed in the enclosure space, is adapted to enter the accommodation space to maintain or replace the equipment component of the airtight equipment, and further adapted to enter the automated maintenance machine to take and place the equipment component.
    Type: Application
    Filed: December 18, 2023
    Publication date: January 2, 2025
    Inventors: CHUNG-PENG HUANG, FANG-YI LIN, KUAN-LIN CHEN, CHUN-CHING KUO
  • Publication number: 20250006440
    Abstract: An airtight switch adapted for an airtight device comprises an enclosure and a lid structure which are adapted to be joined with each other at a junction plane. The airtight switch includes a slider disposed at one of the enclosure or the lid structure. The airtight switch includes a contact element disposed at the other of the enclosure or the lid structure. The contact element has a sloped surface, and the slider selectively abuts against the sloped surface. The airtight switch includes a linear drive device adapted to drive the slider to move linearly in a sliding direction. The sliding direction is parallel to the junction plane and non-perpendicular to a normal vector of the sloped surface. The airtight switch is adapted to be applied in an airtight device needing a switch with good sealing and airtightness.
    Type: Application
    Filed: December 18, 2023
    Publication date: January 2, 2025
    Inventors: CHUNG-PENG HUANG, FANG-YI LIN, KUAN-LIN CHEN, CHUN-CHING KUO
  • Publication number: 20250003669
    Abstract: An exhaust condensation recovery device for solving an issue of difficulties in removing a gaseous working fluid diffused in an outer hood. An exhaust condensation recovery device includes a housing, including a gas inflow portion, a liquid inflow portion and a gas outflow portion, the housing including therein an accommodating chamber, wherein a liquid collection zone is formed below accommodating chamber, and the liquid outflow portion is in communication with the liquid collection zone; and a cooling module, forming a condensation channel in the accommodating chamber, wherein the condensation channel is located above the liquid collection zone, and two ends of the condensation channel are respectively in communication with the gas inflow portion and the gas outflow portion.
    Type: Application
    Filed: February 1, 2024
    Publication date: January 2, 2025
    Inventors: CHUNG-PENG HUANG, FANG-YI LIN, KUAN-LIN CHEN, CHUN-CHING KUO
  • Patent number: 12183722
    Abstract: Disclosed embodiments include molded interconnect bridges that are in a molded frame, where the molded frame includes passive devices that couple to a metal buildup layer that includes at least one power rail and one ground rail. The molded interconnects bridge is embedded in an integrated-circuit package substrate between a die side and a land side, and closer to the die side.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: December 31, 2024
    Assignee: Intel Corporation
    Inventors: Jenny Shio Yin Ong, Seok Ling Lim, Bok Eng Cheah, Jackson Chung Peng Kong
  • Publication number: 20240429131
    Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.
    Type: Application
    Filed: September 4, 2024
    Publication date: December 26, 2024
    Inventors: Bok Eng CHEAH, Choong Kooi CHEE, Jackson Chung Peng KONG, Wai Ling LEE, Tat Hin TAN
  • Publication number: 20240395722
    Abstract: Disclosed embodiments include composite-bridge die-to-die interconnects that are on a die side of an integrated-circuit package substrate and that contacts two IC dice and a passive device that is in a molding material, where the molding material also contacts the two IC dice.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Applicant: Intel Corporation
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Jenny Shio Yin Ong, Ping Ping Ooi, Seok Ling Lim
  • Publication number: 20240397610
    Abstract: An integrated circuit (IC) package includes a via extending through a stack of antipads in a stack of layers, and the stack of antipads has an antipad with a shorter diameter between antipads with longer diameters. The via may have first and second connections and first and second pads at or over and under the antipads. The longer diameters (over and under the shorter diameter) may be equal. Intervening antipads of intermediate size may be between the smallest antipads and the largest antipads. An antipad void profile may be tapered and concave, with flatter slopes nearer the upper and lower ends of the via and steeper slopes near a via midpoint. A second via may be adjacent the first via. One or more other vias may have an aligned (rather than a tapered) profile.
    Type: Application
    Filed: May 24, 2023
    Publication date: November 28, 2024
    Applicant: Intel Corporation
    Inventors: Aik Hong Tan, Jackson Chung Peng Kong, Li Wern Chew
  • Patent number: 12142570
    Abstract: Disclosed embodiments include composite-bridge die-to-die interconnects that are on a die side of an integrated-circuit package substrate and that contacts two IC dice and a passive device that is in a molding material, where the molding material also contacts the two IC dice.
    Type: Grant
    Filed: October 27, 2022
    Date of Patent: November 12, 2024
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Jenny Shio Yin Ong, Ping Ping Ooi, Seok Ling Lim
  • Publication number: 20240370624
    Abstract: An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ting LU, Chih-Chiang Chang, Chung-Peng Hsieh, Chung-Chieh Yang, Yung-Chow Peng, Yung-Shun Chen, Tai-Yi Chen, Nai Chen Cheng
  • Publication number: 20240369627
    Abstract: A device for measuring a frequency response of a wafer is provided. The device includes a first oscillator, a clock generator, a first circuit, and a first driver. The first oscillator configured to provide a first signal having a first frequency. The clock generator is configured to receive the first signal and generate a first clock signal and a second clock signal having the first frequency. The first circuit on the wafer and having a first number of parallelly connected ring oscillators. The first driver is coupled to the first circuit and the clock generator, and configured to receive the first clock signal and the second clock signal, and drive the first circuit. A first portion of each ring oscillator of the first circuit is electrically disconnected from a second portion of each ring oscillator of the first circuit.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 7, 2024
    Inventors: YUNG-SHUN CHEN, CHIH-CHIANG CHANG, CHUNG-PENG HSIEH, YUNG-CHOW PENG
  • Patent number: 12117489
    Abstract: A device for measuring characteristics of a wafer is provided. The device includes a first circuit on the wafer and having a first number of parallelly connected oscillators, and a second circuit on the wafer and having the first number of parallelly connected oscillators; wherein a first portion of the second circuit is disconnected from a second portion of the second circuit.
    Type: Grant
    Filed: September 12, 2020
    Date of Patent: October 15, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yung-Shun Chen, Chih-Chiang Chang, Chung-Peng Hsieh, Yung-Chow Peng
  • Patent number: 12112997
    Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.
    Type: Grant
    Filed: June 29, 2023
    Date of Patent: October 8, 2024
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Choong Kooi Chee, Jackson Chung Peng Kong, Wai Ling Lee, Tat Hin Tan
  • Publication number: 20240321731
    Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.
    Type: Application
    Filed: June 5, 2024
    Publication date: September 26, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hsin HU, Yu-Chiun LIN, Yi-Hsuan CHUNG, Chung-Peng HSIEH, Chung-Chieh YANG, Po-Nien CHEN
  • Patent number: 12080628
    Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: September 3, 2024
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Choong Kooi Chee, Jackson Chung Peng Kong, Wai Ling Lee, Tat Hin Tan