Patents by Inventor Chung-Peng Hsieh
Chung-Peng Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240106425Abstract: A delay-locked loop (DLL) circuit includes a low pass filter coupled to a phase detector, and a digitally controlled delay line (DCDL) coupled to the low pass filter. The DCDL includes an input terminal, an output terminal coupled to an input terminal of the phase detector, and stages that propagate a signal along a first path from the input terminal to a selectable return stage and along a second path from the return stage to the output terminal. Each stage includes first and second inverters that selectively propagate the signal along the first and second paths, a third inverter that selectively propagates the signal from the first path to the second path, and either fourth and fifth inverters that selectively propagate the signal along the first and second paths, or a sixth inverter that selectively propagates the signal from the first path to the second path.Type: ApplicationFiled: December 1, 2023Publication date: March 28, 2024Inventors: Chung-Peng HSIEH, Chih-Chiang CHANG, Yung-Chow PENG
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Patent number: 11855644Abstract: A digitally controlled delay line (DCDL) includes input and output terminals, and a plurality of stages that propagate a signal along a first signal path from the input terminal to a selectable return stage and along a second signal path from the return stage to the output terminal. Each stage includes a first inverter that selectively propagates the signal along the first signal path, a second inverter that selectively propagates the signal along the second signal path, and a third inverter that selectively propagates the signal from the first signal path to the second signal path. At least one of the first or third inverters includes a tuning portion including either a plurality of parallel, independently controllable p-type transistors coupled in series with a single independently controllable n-type transistor, or a plurality of parallel, independently controllable n-type transistors coupled in series with a single independently controllable p-type transistor.Type: GrantFiled: January 18, 2023Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Peng Hsieh, Chih-Chiang Chang, Yung-Chow Peng
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Patent number: 11835551Abstract: A device includes a control circuit, a scope circuit, a first logic gate and a second logic gate. The control circuit is configured to generate a first control signal according to a voltage signal and a delayed signal. The scope circuit is configured to generate a first current signal in response to the first control signal and the voltage signal. The first logic gate is configured to perform a first logical operation on the voltage signal and one of the voltage signal and the delayed signal to generate a second control signal. The second logical gate configured to perform a second logical operation on the second control signal and a test control signal to generate a second current signal.Type: GrantFiled: December 21, 2022Date of Patent: December 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Peng Hsieh, Chih-Chiang Chang, Chung-Chieh Yang
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Patent number: 11686746Abstract: A low power comparator and a self-regulated device for adjusting power saving level of an electronic device are provided. The low power comparator includes an input differential pair circuit, a self-regulated device, and a tail current switch. The input differential pair circuit is configured to receive input signals to be compared. The self-regulated device is coupled to the input differential pair circuit and includes a self-regulated circuit which has a first transistor with a first threshold voltage and a second transistor with a second threshold voltage and is configured to adjust a power saving level of the low-power comparator according to the first threshold voltage and the second threshold voltage. The tail current switch is coupled to the input differential pair circuit through the self-regulated circuit to provide a constant current to the input differential pair circuit.Type: GrantFiled: February 16, 2022Date of Patent: June 27, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Chow Peng, Chung-Peng Hsieh
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Publication number: 20230186008Abstract: An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.Type: ApplicationFiled: February 3, 2023Publication date: June 15, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Ting LU, Chih-Chiang CHANG, Chung-Peng HSIEH, Chung-Chieh YANG, Yung-Chow PENG, Yung-Shun CHEN, Tai-Yi CHEN, Nai Chen CHENG
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Publication number: 20230155583Abstract: A digitally controlled delay line (DCDL) includes input and output terminals, and a plurality of stages that propagate a signal along a first signal path from the input terminal to a selectable return stage and along a second signal path from the return stage to the output terminal. Each stage includes a first inverter that selectively propagates the signal along the first signal path, a second inverter that selectively propagates the signal along the second signal path, and a third inverter that selectively propagates the signal from the first signal path to the second signal path. At least one of the first or third inverters includes a tuning portion including either a plurality of parallel, independently controllable p-type transistors coupled in series with a single independently controllable n-type transistor, or a plurality of parallel, independently controllable n-type transistors coupled in series with a single independently controllable p-type transistor.Type: ApplicationFiled: January 18, 2023Publication date: May 18, 2023Inventors: Chung-Peng HSIEH, Chih-Chiang CHANG, Yung-Chow PENG
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Publication number: 20230122803Abstract: A device includes a control circuit, a scope circuit, a first logic gate and a second logic gate. The control circuit is configured to generate a first control signal according to a voltage signal and a delayed signal. The scope circuit is configured to generate a first current signal in response to the first control signal and the voltage signal. The first logic gate is configured to perform a first logical operation on the voltage signal and one of the voltage signal and the delayed signal to generate a second control signal. The second logical gate configured to perform a second logical operation on the second control signal and a test control signal to generate a second current signal.Type: ApplicationFiled: December 21, 2022Publication date: April 20, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Peng HSIEH, Chih-Chiang CHANG, Chung-Chieh YANG
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Patent number: 11574104Abstract: An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.Type: GrantFiled: December 28, 2020Date of Patent: February 7, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Ting Lu, Chih-Chiang Chang, Chung-Peng Hsieh, Chung-Chieh Yang, Yung-Chow Peng, Yung-Shun Chen, Tai-Yi Chen, Nai Chen Cheng
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Patent number: 11567105Abstract: A device includes a control circuit, a scope circuit, and a time-to-current converter. The control circuit is configured to receive a voltage signal from a voltage-controlled oscillator, delay the voltage signal for a delay time to generate a first control signal, and to generate a second control signal according to the first control signal and the voltage signal. The scope circuit is configured to generate a first current signal in response to the second control signal and the voltage signal. The time-to-current converter is configured generate a second current signal according to the first control signal, the voltage signal, a first switch signal, and a test control signal.Type: GrantFiled: May 20, 2021Date of Patent: January 31, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Peng Hsieh, Chih-Chiang Chang, Chung-Chieh Yang
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Patent number: 11563429Abstract: A digitally controlled delay line (DCDL) includes an input terminal, an output terminal, and a plurality of stages configured to propagate a signal along a first signal path from the input terminal to a selectable return stage of the plurality of stages, and along a second signal path from the return stage of the plurality of stages to the output terminal. Each stage of the plurality of stages includes a first inverter configured to selectively propagate the signal along the first signal path, a second inverter configured to selectively propagate the signal along the second signal path, and a third inverter configured to selectively propagate the signal from the first signal path to the second signal path. Each of the first and third inverters has a tunable selection configuration corresponding to greater than three output states.Type: GrantFiled: July 15, 2021Date of Patent: January 24, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Peng Hsieh, Chih-Chiang Chang, Yung-Chow Peng
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Publication number: 20220170963Abstract: A low power comparator and a self-regulated device for adjusting power saving level of an electronic device are provided. The low power comparator includes an input differential pair circuit, a self-regulated device, and a tail current switch. The input differential pair circuit is configured to receive input signals to be compared. The self-regulated device is coupled to the input differential pair circuit and includes a self-regulated circuit which has a first transistor with a first threshold voltage and a second transistor with a second threshold voltage and is configured to adjust a power saving level of the low-power comparator according to the first threshold voltage and the second threshold voltage. The tail current switch is coupled to the input differential pair circuit through the self-regulated circuit to provide a constant current to the input differential pair circuit.Type: ApplicationFiled: February 16, 2022Publication date: June 2, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Chow Peng, Chung-Peng Hsieh
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Patent number: 11287452Abstract: A low power comparator and a self-regulated device for adjusting power saving level of an electronic device are provided. The low power comparator includes an input differential pair circuit, a self-regulated device, and a tail current switch. The input differential pair circuit is configured to receive input signals to be compared. The self-regulated device is coupled to the input differential pair circuit and includes a self-regulated circuit which has a first transistor with a first threshold voltage and a second transistor with a second threshold voltage and is configured to adjust a power saving level of the low-power comparator according to the first threshold voltage and the second threshold voltage. The tail current switch is coupled to the input differential pair circuit through the self-regulated circuit to provide a constant current to the input differential pair circuit.Type: GrantFiled: September 23, 2020Date of Patent: March 29, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Chow Peng, Chung-Peng Hsieh
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Publication number: 20220082621Abstract: A device for measuring characteristics of a wafer is provided. The device comprises a first circuit on the wafer and having a first number of parallelly connected oscillators, and a second circuit on the wafer and having the first number of parallelly connected oscillators; wherein a first portion of the second circuit is disconnected from a second portion of the second circuit.Type: ApplicationFiled: September 12, 2020Publication date: March 17, 2022Inventors: YUNG-SHUN CHEN, CHIH-CHIANG CHANG, CHUNG-PENG HSIEH, YUNG-CHOW PENG
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Publication number: 20210344334Abstract: A digitally controlled delay line (DCDL) includes an input terminal, an output terminal, and a plurality of stages configured to propagate a signal along a first signal path from the input terminal to a selectable return stage of the plurality of stages, and along a second signal path from the return stage of the plurality of stages to the output terminal. Each stage of the plurality of stages includes a first inverter configured to selectively propagate the signal along the first signal path, a second inverter configured to selectively propagate the signal along the second signal path, and a third inverter configured to selectively propagate the signal from the first signal path to the second signal path. Each of the first and third inverters has a tunable selection configuration corresponding to greater than three output states.Type: ApplicationFiled: July 15, 2021Publication date: November 4, 2021Inventors: Chung-Peng HSIEH, Chih-Chiang CHANG, Yung-Chow PENG
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Publication number: 20210270871Abstract: A device includes a control circuit, a scope circuit, and a time-to-current converter. The control circuit is configured to receive a voltage signal from a voltage-controlled oscillator, delay the voltage signal for a delay time to generate a first control signal, and to generate a second control signal according to the first control signal and the voltage signal. The scope circuit is configured to generate a first current signal in response to the second control signal and the voltage signal. The time-to-current converter is configured generate a second current signal according to the first control signal, the voltage signal, a first switch signal, and a test control signal.Type: ApplicationFiled: May 20, 2021Publication date: September 2, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Peng HSIEH, Chih-Chiang CHANG, Chung-Chieh YANG
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Patent number: 11082035Abstract: A digitally controlled delay line (DCDL) includes an input terminal, an output terminal, and a plurality of stages configured to propagate a signal along a first signal path from the input terminal to a selectable return stage of the plurality of stages, and along a second signal path from the return stage of the plurality of stages to the output terminal. Each stage of the plurality of stages includes first and second inverters configured to selectively propagate the signal along the first signal path, third and fourth inverters configured to selectively propagate the signal along the second signal path, and a fifth inverter configured to selectively propagate the signal from the first signal path to the second signal path.Type: GrantFiled: September 23, 2020Date of Patent: August 3, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Peng Hsieh, Chih-Chiang Chang, Yung-Chow Peng
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Publication number: 20210224459Abstract: An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.Type: ApplicationFiled: December 28, 2020Publication date: July 22, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Ting LU, Chih-Chiang CHANG, Chung-Peng HSIEH, Chung-Chieh YANG, Yung-Chow PENG, Yung-Shun CHEN, Tai-Yi CHEN, Nai Chen CHENG
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Patent number: 11035886Abstract: A device is disclosed that includes a control circuit and a scope circuit. The control circuit is configured to delay a voltage signal to generate a first control signal. The scope circuit is configured to be operated in one of a first mode and a second mode according to the first control signal. In the first mode, the scope circuit is configured to generate a first current signal indicating amplitudes of the voltage signal, and in the second mode, the scope circuit is configured to stop generating the first current signal.Type: GrantFiled: December 6, 2018Date of Patent: June 15, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Peng Hsieh, Chih-Chiang Chang, Chung-Chieh Yang
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Publication number: 20210125890Abstract: A semiconductor device is disclosed. In one example, the semiconductor device includes: an electronic component having a top surface, a bottom surface, and two end portions; a plurality of contacts disposed on the top surface; and a plurality of metal nodes disposed on the plurality of contacts. The plurality of contacts includes two end contacts disposed at the two end portions respectively and at least one intermediate contact disposed between the two end contacts. The plurality of metal nodes includes two end metal nodes disposed on the two end contacts respectively and at least one intermediate metal node disposed on the at least one intermediate contact.Type: ApplicationFiled: January 4, 2021Publication date: April 29, 2021Inventors: Chung-Chieh YANG, Yung-Chow PENG, Chung-Peng HSIEH, Sa-Lly LIU
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Publication number: 20210066193Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.Type: ApplicationFiled: November 16, 2020Publication date: March 4, 2021Inventors: Chia-Hsin HU, Yu-Chiun LIN, Yi-Hsuan CHUNG, Chung-Peng HSIEH, Chung-Chieh YANG, Po-Nien CHEN