Abstract: Embodiments herein relate to a module which can be inserted into or removed from a computing device by a user. The module includes an input-output port which is configured for a desired specification, such as USB-A, USB-C, Thunderbolt, DisplayPort or HDMI. The port can be provided on an expansion card such as an M.2 card for communicating with a host platform. The host platform can communicate with different types of modules in a standardized way so that complexity and costs are reduced. In another aspect, with a dual port module, the host platform can concurrently send/receive power through one port and send/receive data from the other port.

Abstract: A display device includes a bezel annular in shape and a flexible display panel. The flexible display panel includes a display area annular in shape and a pin bonding area connected to the display area. The display area is disposed above the front side of the bezel. The pin bonding 5 area is bent from the front side of the bezel to the outer side of the bezel.

Abstract: The graphics processing unit (GPU) of a processing system transitions to a low-power state between frame rendering operations according to an inter-frame power off process, where GPU state information is stored on retention hardware. The retention hardware can include retention random access memory (RAM) or retention flip-flops. The retention hardware is operable in an active mode and a retention mode, where read/write operations are enabled at the retention hardware in the active mode and disabled in the retention mode, but data stored on the retention hardware is still retained in the retention mode. The retention hardware is placed in the retention state between frame rendering operations. The GPU transitions from its low-power state to its active state upon receiving an indication that a new frame is ready to be rendered and is restored using the GPU state information stored at the retention hardware.

Abstract: The graphics processing unit (GPU) of a processing system transitions to a low-power state between frame rendering operations according to an inter-frame power off process, where GPU state information is stored on retention hardware. The retention hardware can include retention random access memory (RAM) or retention flip-flops. The retention hardware is operable in an active mode and a retention mode, where read/write operations are enabled at the retention hardware in the active mode and disabled in the retention mode, but data stored on the retention hardware is still retained in the retention mode. The retention hardware is placed in the retention state between frame rendering operations. The GPU transitions from its low-power state to its active state upon receiving an indication that a new frame is ready to be rendered and is restored using the GPU state information stored at the retention hardware.

Abstract: A lead frame is disclosed. In an embodiment, the lead frame includes a frame having a plurality of lead frame sections, wherein the lead frame sections are connected to the frame, wherein the frame has at least two longitudinal sides and at least two transverse sides, wherein at least in one longitudinal side includes an imprint, and wherein the imprint bolsters stability of the longitudinal side against sagging.

Abstract: A lead frame is disclosed. In an embodiment, the lead frame includes a frame having a plurality of lead frame sections, wherein the lead frame sections are connected to the frame, wherein the frame has at least two longitudinal sides and at least two transverse sides, wherein at least in one longitudinal side includes an imprint, and wherein the imprint bolsters stability of the longitudinal side against sagging.

Abstract: A filter configuration including a substrate, a primary microstrip line and a first defected ground structure is disclosed. The substrate has a first face and a second face. The second face is a ground face. The primary microstrip line is arranged on the first face and extends in a first direction. The first defected ground structure is arranged on the second face. The first defected ground structure includes a first section, a first circular section, a second section, a second circular section and a third section that are connected to each other in sequence in a second direction perpendicular to the first direction. The second section is covered by the primary microstrip line in a vertical direction perpendicular to the first and second faces. The primary microstrip line has a width equal to a minimum length of the second section. As such, the filtering effect can be improved.

Abstract: A step impedance resonator filter including a first resonator and a second resonator is disclosed. The first resonator includes a first coupled line and a first tapped line connected to the first coupled line. The second resonator includes a second coupled line and a second tapped line connected to the second coupled line. The second coupled line is coupled with the first coupled line. The first tapped line has a first central line which is spaced from an end face of the first coupled line at a first distance. The second tapped line has a second central line which is spaced from an end face of the second coupled line at a second distance. The first distance is larger than the second distance. As such, the performance of the step impedance resonator filter can be improved.

Abstract: A filter configuration including a substrate, a primary microstrip line and a first defected ground structure is disclosed. The substrate has a first face and a second face. The second face is a ground face. The primary microstrip line is arranged on the first face and extends in a first direction. The first defected ground structure is arranged on the second face. The first defected ground structure includes a first section, a first circular section, a second section, a second circular section and a third section that are connected to each other in sequence in a second direction perpendicular to the first direction. The second section is covered by the primary microstrip line in a vertical direction perpendicular to the first and second faces. The primary microstrip line has a width equal to a minimum length of the second section. As such, the filtering effect can be improved.

Abstract: A step impedance resonator filter including a first resonator and a second resonator is disclosed. The first resonator includes a first coupled line and a first tapped line connected to the first coupled line. The second resonator includes a second coupled line and a second tapped line connected to the second coupled line. The second coupled line is coupled with the first coupled line. The first tapped line has a first central line which is spaced from an end face of the first coupled line at a first distance. The second tapped line has a second central line which is spaced from an end face of the second coupled line at a second distance. The first distance is larger than the second distance. As such, the performance of the step impedance resonator filter can be improved.

Abstract: A method and apparatus for register packing prior to register renaming in a microprocessor are provided. The method includes: receiving a plurality of micro operations (micro-ops) decoded from one or more instructions; packing a plurality of registers which are included in the micro-ops into a packed register structure including a plurality of packed registers based on a preset number of rename ports of a renamer through which the packed registers are read or written for register renaming; and sending the packed registers for register renaming.

Abstract: An improved keypad and speaker assembly is provided. The assembly (100) comprises a speaker grille formed of torturous porting (220), and a keyboard (108) comprising audio slots (120) which are offset beneath the tortuous porting (220). The speaker (104) is aligned beneath the keyboard (108). The tortuous porting (220) and audio slots (120) provide an unobstructed air passage/path between the speaker and ambient while protecting against water intrusion.

Abstract: For a memory access at a processor, only a subset (less than all) of the ways of a cache associated with a memory address is prepared for access. The subset of ways is selected based on stored information indicating, for each memory access, which corresponding way of the cache was accessed. The subset of ways is selected and preparation of the subset of ways is initiated prior to the final determination as to which individual cache way in the subset is to be accessed.

Abstract: An improved keypad and speaker assembly is provided. The assembly (100) comprises a speaker grille formed of torturous porting (220), and a keyboard (108) comprising audio slots (120) which are offset beneath the tortuous porting (220). The speaker (104) is aligned beneath the keyboard (108). The tortuous porting (220) and audio slots (120) provide an unobstructed air passage/path between the speaker and ambient while protecting against water intrusion.

Abstract: A method and apparatus for register packing prior to register renaming in a microprocessor are provided. The method includes: receiving a plurality of micro operations (micro-ops) decoded from one or more instructions; packing a plurality of registers which are included in the micro-ops into a packed register structure including a plurality of packed registers based on a preset number of rename ports of a renamer through which the packed registers are read or written for register renaming; and sending the packed registers for register renaming.

Abstract: For a memory access at a processor, only a subset (less than all) of the ways of a cache associated with a memory address is prepared for access. The subset of ways is selected based on stored information indicating, for each memory access, which corresponding way of the cache was accessed. The subset of ways is selected and preparation of the subset of ways is initiated prior to the final determination as to which individual cache way in the subset is to be accessed.

Abstract: A method and circuit for fast flag generation. The circuit is coupled to receive data to be shifted, the data including a first plurality of bits. A shift count value (including a second plurality of bits) is also received by the circuit, as well as an indication of a direction the data is to be shifted. Based on the shift count value and the indication of direction, the position of a bit within the data is determined. The bit is then output as a flag bit.

Abstract: Various embodiments of methods and systems for storing multiple groups of microcode operations and corresponding control sequences per row of microcode ROM are disclosed. In one embodiment, an integrated circuit may include a microcode ROM coupled to a control sequence logic unit. The microcode ROM may store multiple groups of microcode operations per row. For each group of microcode operations stored in a row, a corresponding control sequence may also be stored in the row. Each group of microcode operations may be included in a microcode routine. The groups of microcode operations stored in a row may be included in the same microcode routine, or some of the groups may be included in different microcode routines.

Abstract: A method and mechanism for performing division. A processor includes a divider configured to perform arithmetic division operations. Prior to dividing a dividend by a divisor, the divider manipulates the dividend and divisor to reduce the number of bits considered and the computations required to perform the division. The divisor is normalized by eliminating sign bits. The dividend is prescaled to eliminate one or more sign bits. Prescaling of the dividend may not be precise as sign bits of the dividend may be shifted out as groups of bits, rather than individual bits. Prescaling of the dividend may be adjusted to account for the fact that the divider considers multiple bits of the dividend at a time. Subsequent to prescaling and adjustment, the dividend may be adjusted in dependence upon the normalization of the divisor. Further adjustment may be utilized to maintain a significance relationship between the divisor and dividend. Subsequent to further adjustment, the division operation may be completed.