Abstract: A light emitting module driver circuit utilized for driving a light emitting module includes a voltage dividing module, a short circuit detection module, and a driving module. A method of performing short circuit protection in the light emitting module driver circuit includes disabling the driving module during a dimming off cycle of the light emitting module driver circuit, enabling the voltage dividing module during the dimming off cycle, dividing a voltage of the light emitting module to generate a divided voltage during the dimming off cycle, and generating a short circuit protection signal according to the divided voltage during the dimming off cycle.

Abstract: A method and a system for producing a panoramic image are provided. The method comprises the following steps. A plurality of original images are obtained. A plurality of pixel blocks corresponding to a plurality of view angles are captured from each of the original images, wherein the number of the view angles is larger than or equal to 2. Part of the pixel blocks which are corresponding to one of the view angles are connected along a connecting direction to result in a single-view panoramic image, wherein the step of connecting part of the pixel blocks are performed repeatedly to result in a plurality of single-view panoramic images.

Abstract: A driving integrated circuit of light emitting diodes is used for driving a plurality of series of light emitting diodes. The driving integrated circuit includes a current setting pin, a regulator circuit, and an adjuster. The driving integrated circuit sets a target current for a current flowing through the plurality of series of light emitting diodes according to an outflowing current of the current setting pin. The adjuster adjusts a target voltage according to the outflowing current. Then the regulator circuit provides a supply voltage for driving the plurality of series of light emitting diodes, so as to regulate a terminal voltage of the plurality of series of light emitting diodes to the target voltage.

Abstract: An image-shooting method with guide for taking stereo images is used in a camera system. The camera system utilizes a same lens to take images. The method includes the following steps. A shooting mode is selected. A guiding information is provided by a display unit. A set of images for a target image field is taken by moving the lens to multiple guiding locations according to the guiding information, in which the set of images is at least two view-angle images with different view angles. The view-angle images are corrected with a stereo visual effect. The set of view-angle images is output, and meanwhile, a corresponding shooting information is output. Then, the view-angle images are adjusted according to the shooting information, so as to achieve a desirable stereo display effect.

Abstract: A driving integrated circuit of light emitting diodes is used for driving at least one light emitting diode. The driving integrated circuit includes a current setting pin, a regulator circuit, and an adjuster. The driving integrated circuit sets a target current for a current flowing through the at least one light emitting diode according to an outflowing current of the current setting pin. The adjuster adjusts a target voltage according to the outflowing current. Then the regulator circuit provides a supply voltage for driving the light emitting diode so as to regulate a terminal voltage of the light emitting diode to the target voltage.

Abstract: Architecture and method of hybrid P2P/client-server for data transmission involve using a P2P grouping method to determine the data transmission mode being a P2P mode or a client-server mode by an original source, for a plurality of peers connected to the original source. The original source further divides the plurality of peers into a P2P group and a client-server group, and dynamically determines the respective number of peers and the upstream bandwidth for the two groups. Thereby, during a data transmission procedure, it may achieve a performance balance among the propagation delay, restriction of upstream bandwidth for data sources, network throughput and system loading.

Abstract: A frequency dividing circuit performs a frequency dividing operation on N input clock signals to obtain N output clock signals, wherein N is a natural number greater than 1. The frequency dividing circuit includes a frequency divider and a flip-flop. The frequency divider samples an initial signal according to a first input clock signal of the N input clock signals to accordingly generate a first output clock signal of the N output clock signals. The initial signal corresponds with an inverse signal of the first output clock signal. The flip-flop samples the first output clock signal to accordingly generate a second output clock signal of the N output clock signals according to a second input clock signal of the N input clock signals.

Abstract: A low dropout regulator having a power transistor, a current-voltage converting circuit, a current variation sensing circuit and a compensation circuit is provided. The power transistor has a power terminal receiving an input voltage, a control terminal, and an output terminal coupled to the current-voltage converting circuit to generate an output voltage. The current variation sensing circuit provides a first and a second output terminal and, according to a current variation of the power transistor, the first and second output terminals vary with distinct voltage transition speeds. The compensation circuit controls the control terminal of the power transistor to adjust the output voltage according to a first voltage difference between a feedback of the output voltage and a reference voltage and a second voltage difference between the second and first output terminals of the current variation sensing circuit.

Abstract: A scheduling method for peer-to-peer data transmission suitable for a peer-to-peer system is described. The peer-to-peer system comprises a plurality of nodes, and the nodes comprise an ith and jth nodes, wherein the jth node uploads a plurality of upload files to the nodes connected thereto, and the upload files comprise an upload file Fij. The scheduling method determines a distributed upload bandwidth Uij of the upload file Fij according to at least one of a plurality of file sizes of the upload files and at least one of the time differences between a plurality of playback deadlines of the upload files and a current transmission time.

Abstract: Presented are methods and systems for providing bandwidth estimation and correction in a communications network. Bandwidth estimation and correction can include calculating a round trip time (RTT) value and a packet loss rate (PLR) value for each packet of a set of packets transmitted at different points in time from a server to a client terminal over the communications network; determining a bandwidth estimate based on the RTT and PLR values for the set of packets transmitted; determining a bandwidth measurement based on the RTT and PLR values for the set of packets; and determining a corrected bandwidth estimate based on the bandwidth estimate and the bandwidth measurement.

Abstract: A power amplifier including a loop filter, a frequency generator, a quantizer, and an output stage module is provided. The frequency generator outputs a signal with a reference frequency to the loop filter, and includes a logic circuit, a current array, and a dummy load. The dummy load representing a load circuit in the loop filter is coupled to the current array. An equivalent impedance of the dummy load is proportioned to an equivalent impedance of the load circuit. The current array outputs the signal and a dummy signal to the loop filter and the dummy load, respectively, according to a logic signal. By using the frequency generator to modulate the frequency automatically, an impact on the power amplifier caused by passive devices therein due to process variationscan be reduced.

Abstract: A frequency dividing circuit performs a frequency dividing operation on N input clock signals to obtain N output clock signals, wherein N is a natural number greater than 1. The frequency dividing circuit includes a frequency divider and a flip-flop. The frequency divider samples an initial signal according to a first input clock signal of the N input clock signals to accordingly generate a first output clock signal of the N output clock signals. The initial signal corresponds with an inverse signal of the first output clock signal. The flip-flop samples the first output clock signal to accordingly generate a second output clock signal of the N output clock signals according to a second input clock signal of the N input clock signals.

Abstract: A sigma delta class D power amplifier includes a loop filter, a quantizer, and an output stage. The quantizer is coupled to the loop filter and quantifies an error signal according to levels of two reference signals to output a pair of mean signals, wherein different logic combinations of the mean signals belong to one of three quantum states. The output stage is coupled to the quantizer and outputs a corresponding output signal according to the different quantum states to drive a load, wherein a driving current of the output signal belongs to one of the three driving states which include at least a steady state with no current of a power amplifier.

Abstract: A power amplifier including a loop filter, a frequency generator, a quantizer, and an output stage module is provided. The frequency generator outputs a signal with a reference frequency to the loop filter, and includes a logic circuit, a current array, and a dummy load. The dummy load representing a load circuit in the loop filter is coupled to the current array. An equivalent impedance of the dummy load is proportioned to an equivalent impedance of the load circuit. The current array outputs the signal and a dummy signal to the loop filter and the dummy load, respectively, according to a logic signal. By using the frequency generator to modulate the frequency automatically, an impact on the power amplifier caused by passive devices therein due to process variationscan be reduced.

Abstract: A sigma delta class D power amplifier includes a loop filter, a quantizer, and an output stage. The quantizer is coupled to the loop filter and quantifies an error signal according to levels of two reference signals to output a pair of mean signals, wherein different logic combinations of the mean signals belong to one of three quantum states. The output stage is coupled to the quantizer and outputs a corresponding output signal according to the different quantum states to drive a load, wherein a driving current of the output signal belongs to one of the three driving states which include at least a steady state with no current of a power amplifier.

Abstract: A power supply apparatus and an operation-mode determining unit and a method thereof are provided. The power supply apparatus includes first and second control units, a switching unit, a power output unit, and an operation-mode determining unit. The first and second control units provide first and second control signals respectively. The switching unit selects to output the first or second control signal according to a switching signal. The power output unit adjusts its output power in accordance with the control signal output from the switching unit. The operation-mode determining unit compares an operation frequency in the power output unit with a reference frequency, and detects an inductor current in the power output unit. The operation-mode determining unit determines the state of a switching signal and outputs it to the switching unit in accordance with the comparison result and the detection result.

Abstract: A manipulation input device structure includes a foundation base and an operating base. The foundation base has a rotation slot, such that the operating base is pivoted therein, and the operating base may relatively pivots to the foundation base and is fixed at a using position or a packaging position. When the operating base pivotally rotates to the packaging position, a space occupied by the manipulation input device is smaller than a space occupied by the manipulation input device when the operating base is located on the using position.

Abstract: Presented are methods and systems for providing bandwidth estimation and correction in a communications network. Bandwidth estimation and correction can include calculating a round trip time (RTT) value and a packet loss rate (PLR) value for each packet of a set of packets transmitted at different points in time from a server to a client terminal over the communications network; determining a bandwidth estimate based on the RTT and PLR values for the set of packets transmitted; determining a bandwidth measurement based on the RTT and PLR values for the set of packets; and determining a corrected bandwidth estimate based on the bandwidth estimate and the bandwidth measurement.

Abstract: A power amplifier including a delta-sigma modulation module, a differential programmable dead-time-control module, and an output stage module is provided. The delta-sigma modulation module integrates and quantizes an error between a differential-mode input signal and an output signal to generate a first and a second mean signal. The differential programmable dead-time-control module includes a first and a second dead-time-control module which respectively generate a first and a second signal corresponding to the first mean signal and a third and a fourth signals corresponding to the second mean signal through logic calculations. The differential programmable dead-time-control module determines a dead time between the first signal and the second signal according to a first control signal and a dead time between the third signal and the fourth signal according to a second control signal. The output stage module generates the output signal according to the first, second, third, and fourth signal.

Abstract: A power amplifier including a delta-sigma modulation module, a differential programmable dead-time-control module, and an output stage module is provided. The delta-sigma modulation module integrates and quantizes an error between a differential-mode input signal and an output signal to generate a first and a second mean signal. The differential programmable dead-time-control module includes a first and a second dead-time-control module which respectively generate a first and a second signal corresponding to the first mean signal and a third and a fourth signals corresponding to the second mean signal through logic calculations. The differential programmable dead-time-control module determines a dead time between the first signal and the second signal according to a first control signal and a dead time between the third signal and the fourth signal according to a second control signal. The output stage module generates the output signal according to the first, second, third, and fourth signal.