Abstract: A structure of field-effect transistor includes a silicon layer of a silicon-on-insulator structure. A gate structure layer in a line shape is disposed on the silicon layer, wherein the gate structure layer includes a first region and a second region abutting to the first region. Trench isolation structures in the silicon layer are disposed at two sides of the gate structure layer, corresponding to the second region. The second region of the gate structure layer is disposed on the silicon layer and overlaps with the trench isolation structure. A source region and a drain region are disposed in the silicon layer at the two sides of the gate structure layer, corresponding to the first region. The second region of the gate structure layer includes a conductive-type junction portion.

Abstract: A structure of field-effect transistor includes a silicon layer of a silicon-on-insulator structure. A gate structure layer in a line shape is disposed on the silicon layer, wherein the gate structure layer includes a first region and a second region abutting to the first region. Trench isolation structures in the silicon layer are disposed at two sides of the gate structure layer, corresponding to the second region. The second region of the gate structure layer is disposed on the silicon layer and overlaps with the trench isolation structure. A source region and a drain region are disposed in the silicon layer at the two sides of the gate structure layer, corresponding to the first region. The second region of the gate structure layer includes a conductive-type junction portion.

Abstract: A structure of field-effect transistor includes a silicon layer of a silicon-on-insulator structure. A gate structure layer in a line shape is disposed on the silicon layer, wherein the gate structure layer includes a first region and a second region abutting to the first region. Trench isolation structures in the silicon layer are disposed at two sides of the gate structure layer, corresponding to the second region. The second region of the gate structure layer is disposed on the silicon layer and overlaps with the trench isolation structure. A source region and a drain region are disposed in the silicon layer at the two sides of the gate structure layer, corresponding to the first region. The second region of the gate structure layer includes a conductive-type junction portion.

Abstract: A MEMS structure includes a substrate, an inter-dielectric layer on a front side of the substrate, a MEMS component on the inter-dielectric layer, and a chamber disposed within the inter-dielectric layer and through the substrate. The chamber has an opening at a backside of the substrate. An etch stop layer is disposed within the inter-dielectric layer. The chamber has a ceiling opposite to the opening and a sidewall joining the ceiling. The sidewall includes a portion of the etch stop layer.

Abstract: Disclosed is a method for improving transmittance of flat or curved liquid crystal display panel. The method includes the following steps. (1) A substrate is manufactured according to the BPS technology. The substrate includes an array substrate and a CF substrate. A spacer and a black matrix are provided on a side of the array substrate and a transparent conductive electrode film is provided on a side of the CF substrate. (2) Marks are engraved on designated positions of the CF substrate by means of a laser and the CF substrate is aligned with the marks on a platform of a UV2A exposure machine. (3) Tracking lines are engraved on the transparent conductive electrode film and a region bounded by the tracking lines is aligned with a light-shielding region of a gate line or a light-shielding region of a data line on the side of the array substrate. (4) The substrate is exposed to light and a mask is used to track the tracking lines.

Abstract: A method for manufacturing a semiconductor structure includes the following steps. First, a semiconductor substrate including a first semiconductor material is provided. The semiconductor substrate includes a dielectric structure formed thereon, and the dielectric structure includes at least a recess formed therein. A first epitaxial layer is then formed in the recess. The first epitaxial layer includes at least a second semiconductor material that a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. Subsequently, a thermal oxidation process is performed to the first epitaxial layer thereby forming a semiconductor layer at a bottom of the recess and a silicon oxide layer on the semiconductor layer. After removing the silicon oxide layer, a second epitaxial layer is formed on the semiconductor layer in the recess.

Abstract: The present invention provides a semiconductor structure, the semiconductor structure includes a substrate defining a memory region and a transistor region, an insulating layer is disposed on the substrate, a 2D material layer disposed on the insulating layer, and disposed within the memory and the transistor region, parts of the 2D material layer within the transistor region is used as the channel region of a transistor structure, the transistor structure is disposed on the channel region. And a resistive random access memory (RRAM) located in the memory region, the RRAM includes a lower electrode layer, a resistance transition layer and an upper electrode layer being sequentially located on the 2D material layer and electrically connected to the channel region.

Abstract: Disclosed is a method for improving transmittance of flat or curved liquid crystal display panel. The method includes the following steps. (1) A substrate is manufactured according to the BPS technology. The substrate includes an array substrate and a CF substrate. A spacer and a black matrix are provided on a side of the array substrate and a transparent conductive electrode film is provided on a side of the CF substrate. (2) Marks are engraved on designated positions of the CF substrate by means of a laser and the CF substrate is aligned with the marks on a platform of a UV2A exposure machine. (3) Tracking lines are engraved on the transparent conductive electrode film and a region bounded by the tracking lines is aligned with a light-shielding region of a gate line or a light-shielding region of a data line on the side of the array substrate. (4) The substrate is exposed to light and a mask is used to track the tracking lines.

Abstract: A semiconductor device includes a silicon substrate, a fin shaped structure and a shallow trench isolation. The fin shaped structure includes a top portion which protrudes from a bottom surface of the fin shaped structure and the fin shaped structure is directly disposed on the silicon substrate. The bottom surface of the fin shaped structure covers an entire top surface of the silicon substrate. The fin shaped structure further includes a silicon germanium (SiGe) layer extending within the fin shaped structure and occupying the whole top portion of the shaped structure. The fin shaped structure is a semiconductor fin shaped structure, and the material of the silicon substrate is different from the material of the silicon germanium layer The shallow trench isolation is disposed on the top portion and the bottom surface of the fin shaped structure.

Abstract: A quantum dot lighting device includes a quantum-dot-lighting layer and two main structural layers being arranged at two sides of the quantum-dot-lighting layer along a vertical direction. The quantum-dot-lighting layer includes a red lighting unit, a green lighting unit, and a red lighting unit. The red lighting unit includes red quantum dots, the green lighting unit includes green quantum dots, and the blue lighting unit includes blue quantum dots. A number of the blue quantum dots is larger than the number of the green quantum dots, and the number of the green quantum dots is larger than the number of the red quantum dots. With the configuration, the material of the quantum dots may be reduced, and the pureness of the white light beams may be enhanced.

Abstract: A display panel and a method for manufacturing the same are disclosed. The display panel includes a color filter substrate, a liquid crystal layer, and a thin film transistor array substrate. Each of pixel units of the thin film transistor array substrate includes a first, second, third, and fourth domains. Liquid crystal molecules corresponding to the first, second, third, and fourth domains respectively have a first, second, third, and fourth pretilt angles. The present invention can increase the display quality of the display panel at the observation viewing angles with the large viewing angles.

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a silicon substrate, a fin shaped structure and a shallow trench isolation. The fin shaped structure is disposed on the silicon substrate and includes a silicon germanium (SiGe) layer extending from bottom to top in the fin shaped structure. The shallow trench isolation covers a bottom portion of the fin shaped structure.

Abstract: The present disclosure relates to a gray-tone mask (GTM) and the manufacturing method thereof. The GTM includes at least one first light-blocking bar and at least on second light-blocking bar. A first gap is formed between any two adjacent first light-blocking bars. The second light-blocking bar is arranged within the first gap. The first gap includes a first crack being formed between adjacent first light-blocking bar and second light-blocking bar, wherein a length of the second light-blocking bar is “a”, a width of the first crack is “b”, and a ratio of the length of the second light-blocking bar (“a”) to the width of the first crack (“b”) satisfy the relationship: 0.9<a/b<1.1. In this way, the design scope is limited. Thus, a reasonable GTM design may be obtain and the experimental cost may be reduced.

Abstract: A method for manufacturing a semiconductor structure includes the following steps. First, a semiconductor substrate including a first semiconductor material is provided. The semiconductor substrate includes a dielectric structure formed thereon, and the dielectric structure includes at least a recess formed therein. A first epitaxial layer is then formed in the recess. The first epitaxial layer includes at least a second semiconductor material that a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. Subsequently, a thermal oxidation process is performed to the first epitaxial layer thereby forming a semiconductor layer at a bottom of the recess and a silicon oxide layer on the semiconductor layer. After removing the silicon oxide layer, a second epitaxial layer is formed on the semiconductor layer in the recess.

Abstract: A semiconductor structure includes a semiconductor substrate, at least a semiconductor layer formed on the semiconductor substrate, and at least a fin structure formed on the semiconductor layer. The semiconductor substrate includes a first semiconductor material, the semiconductor layer includes the first semiconductor material and a second semiconductor material, and the fin structure includes at least the first semiconductor material. A lattice constant of the second semiconductor material is different from a lattice constant of the first semiconductor material. The semiconductor layer includes a first width, the fin structure includes a second width, and the second width is smaller than the first width.

Abstract: A fetal movement measuring device includes a wearable article to be worn on a pregnant woman's abdomen, plural measurement units, and a mobile device pre-installed with a fetal movement algorithm. The measurement units are provided separately on the outer surface of the wearable article and each include a fetal movement sensor for sensing a dynamic physiological signal of the abdomen and a power supply element for supplying necessary electricity to the fetal movement sensor. The dynamic physiological signals sensed by the fetal movement sensors are received by the mobile device, processed with the fetal movement algorithm, and rid of synchronous signal components. Then, the fetal movement algorithm performs calculation on the remaining signal components to generate fetal movement information, which includes a fetal movement location and a fetal movement magnitude. Thus, each fetal movement is measured in a non-contact manner, and its location, obtained through asynchronous multipoint measurement.

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a silicon substrate, a fin shaped structure and a shallow trench isolation. The fin shaped structure is disposed on the silicon substrate and includes a silicon germanium (SiGe) layer extending downwardly from a top end and at least occupying 80% to 90% of the fin shaped structure. The shallow trench isolation covers a bottom portion of the fin shaped structure.

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a silicon substrate, a fin shaped structure and a shallow trench isolation. The fin shaped structure is disposed on the silicon substrate and includes a silicon germanium (SiGe) layer extending from bottom to top in the fin shaped structure. The shallow trench isolation covers a bottom portion of the fin shaped structure.

Abstract: A semiconductor device includes a silicon substrate, a fin shaped structure and a shallow trench isolation. The fin shaped structure includes a top portion which protrudes from a bottom surface of the fin shaped structure and the fin shaped structure is directly disposed on the silicon substrate. The bottom surface of the fin shaped structure covers an entire top surface of the silicon substrate. The fin shaped structure further includes a silicon germanium (SiGe) layer extending within the fin shaped structure and occupying the whole top portion of the shaped structure. The fin shaped structure is a semiconductor fin shaped structure, and the material of the silicon substrate is different from the material of the silicon germanium layer The shallow trench isolation is disposed on the top portion and the bottom surface of the fin shaped structure.

Abstract: A quantum dot lighting device includes a quantum-dot-lighting layer and two main structural layers being arranged at two sides of the quantum-dot-lighting layer along a vertical direction. The quantum-dot-lighting layer includes a red lighting unit, a green lighting unit, and a red lighting unit. The red lighting unit includes red quantum dots, the green lighting unit includes green quantum dots, and the blue lighting unit includes blue quantum dots. A number of the blue quantum dots is larger than the number of the green quantum dots, and the number of the green quantum dots is larger than the number of the red quantum dots.