Patents by Inventor Chung-Ying Yang
Chung-Ying Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240136447Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, a first deep well region, at least two second well regions, at least one isolation structure and an implantation region. The first deep well region is disposed in the semiconductor substrate, wherein the first deep well region has a first conductivity type. The second well regions are disposed on the first deep well region, wherein the second well regions have a second conductivity type. The isolation structure covers a portion of the first deep well region and surrounds at least a portion of the second well regions. The implantation region is located under a top surface of the semiconductor substrate, wherein the implantation region has a discontinuous portion, and the discontinuous portion partially overlaps the first deep well region.Type: ApplicationFiled: October 24, 2022Publication date: April 25, 2024Applicant: Vanguard International Semiconductor CorporationInventors: Chung-Ren LAO, Hsiao-Ying YANG, Hsing-Chao LIU, Ching-Chung CHEN
-
Patent number: 10998277Abstract: A customized seal ring for a semiconductor device is formed of multiple seal ring cells that are selected and arranged to produce a seal ring design. The cells include first cells that are coupled to ground and second cells that are not coupled to ground. The second cells that are not coupled to ground, include a higher density of metal features in an inner portion thereof, than the first seal ring cells. Dummy metal vias and other metal features that may be present in the inner portion of the second seal ring cells are absent from the inner portion of the first seal ring cells that are coupled to ground. The seal ring design may include various arrangements, including alternating and repeating sequences of the different seal ring cells.Type: GrantFiled: June 17, 2019Date of Patent: May 4, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsien-Wei Chen, Chung-Ying Yang
-
Publication number: 20190304932Abstract: A customized seal ring for a semiconductor device is formed of multiple seal ring cells that are selected and arranged to produce a seal ring design. The cells include first cells that are coupled to ground and second cells that are not coupled to ground. The second cells that are not coupled to ground, include a higher density of metal features in an inner portion thereof, than the first seal ring cells. Dummy metal vias and other metal features that may be present in the inner portion of the second seal ring cells are absent from the inner portion of the first seal ring cells that are coupled to ground. The seal ring design may include various arrangements, including alternating and repeating sequences of the different seal ring cells.Type: ApplicationFiled: June 17, 2019Publication date: October 3, 2019Inventors: Hsien-Wei Chen, Chung-Ying Yang
-
Patent number: 10325864Abstract: A customized seal ring for a semiconductor device is formed of multiple seal ring cells that are selected and arranged to produce a seal ring design. The cells include first cells that are coupled to ground and second cells that are not coupled to ground. The second cells that are not coupled to ground, include a higher density of metal features in an inner portion thereof, than the first seal ring cells. Dummy metal vias and other metal features that may be present in the inner portion of the second seal ring cells are absent from the inner portion of the first seal ring cells that are coupled to ground. The seal ring design may include various arrangements, including alternating and repeating sequences of the different seal ring cells.Type: GrantFiled: September 23, 2016Date of Patent: June 18, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsien-Wei Chen, Chung-Ying Yang
-
Publication number: 20170012005Abstract: A customized seal ring for a semiconductor device is formed of multiple seal ring cells that are selected and arranged to produce a seal ring design. The cells include first cells that are coupled to ground and second cells that are not coupled to ground. The second cells that are not coupled to ground, include a higher density of metal features in an inner portion thereof, than the first seal ring cells. Dummy metal vias and other metal features that may be present in the inner portion of the second seal ring cells are absent from the inner portion of the first seal ring cells that are coupled to ground. The seal ring design may include various arrangements, including alternating and repeating sequences of the different seal ring cells.Type: ApplicationFiled: September 23, 2016Publication date: January 12, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsien-Wei CHEN, Chung-Ying YANG
-
Patent number: 9478505Abstract: A customized seal ring for a semiconductor device is formed of multiple seal ring cells that are selected and arranged to produce a seal ring design. The cells include first cells that are coupled to ground and second cells that are not coupled to ground. The second cells that are not coupled to ground, include a higher density of metal features in an inner portion thereof, than the first seal ring cells. Dummy metal vias and other metal features that may be present in the inner portion of the second seal ring cells are absent from the inner portion of the first seal ring cells that are coupled to ground. The seal ring design may include various arrangements, including alternating and repeating sequences of the different seal ring cells.Type: GrantFiled: April 12, 2012Date of Patent: October 25, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsien-Wei Chen, Chung-Ying Yang
-
Patent number: 9337117Abstract: A package comprises a semiconductor device. The semiconductor device comprises an active surface and side surfaces. The active surface has a contact pad. The package also comprises a mold covering the side surfaces of the semiconductor device. The package further comprises an interconnection line coupled with the contact pad and extending over the active surface of the semiconductor device. The package additionally comprises an under-bump metallurgy (UBM) layer over the interconnection line. The package also comprises a seal ring structure extending around and outside an upper periphery of the semiconductor device on the mold, the seal ring structure comprising a seal layer extending on a same level as at least one of the interconnection line or the UBM layer.Type: GrantFiled: December 23, 2014Date of Patent: May 10, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Ying Yang, Hsien-Wei Chen, Tsung-Yuan Yu, Shih-Wei Liang
-
Patent number: 9236322Abstract: Apparatus and methods for forming a heat spreader on a substrate to release heat for a semi-conductor package are disclosed. The apparatus comprises a substrate. A dielectric layer is formed next to the substrate and in contact with a surface of the substrate. A heat spreader is formed next to the substrate and in contact with another surface of the substrate. A passivation layer is formed next to the dielectric layer. A connection pad is placed on top of the passivation layer. The substrate may comprise additional through-silicon-vias. The contact surface between the substrate and the heat spreader may be a scraggy surface. The packaging method further proceeds to connect a chip to the connection pad by way of a connection device such as a solder ball or a bump.Type: GrantFiled: April 11, 2012Date of Patent: January 12, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Wei Chen, Chung-Ying Yang, Chao-Wen Shih, Kai-Chiang Wu
-
Patent number: 9117831Abstract: A semiconductor device includes a substrate having a circuit region and a seal ring region. The seal ring region surrounds the circuit region. A seal ring structure is disposed over the seal ring region. The seal ring structure has a first portion and a second portion above the first portion. The first portion has a width W1, and the second portion has a width W2. The width W1 is less than the width W2.Type: GrantFiled: January 11, 2011Date of Patent: August 25, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ching-Jung Yang, Yu-Wen Liu, Michael Shou-Ming Tong, Hsien-Wei Chen, Chung-Ying Yang, Tsung-Yuan Yu
-
Publication number: 20150206817Abstract: A package comprises a semiconductor device. The semiconductor device comprises an active surface and side surfaces. The active surface has a contact pad. The package also comprises a mold covering the side surfaces of the semiconductor device. The package further comprises an interconnection line coupled with the contact pad and extending over the active surface of the semiconductor device. The package additionally comprises an under-bump metallurgy (UBM) layer over the interconnection line. The package also comprises a seal ring structure extending around and outside an upper periphery of the semiconductor device on the mold, the seal ring structure comprising a seal layer extending on a same level as at least one of the interconnection line or the UBM layer.Type: ApplicationFiled: December 23, 2014Publication date: July 23, 2015Inventors: Chung-Ying YANG, Hsien-Wei CHEN, Tsung-Yuan YU, Shih-Wei LIANG
-
Patent number: 9064939Abstract: A method of making an integrated circuit including forming a seal ring structure around a circuit where the seal ring structure has a first portion and a tilted portion. The first portion of the seal ring structure is substantially parallel with an edge of the circuit. The tilted portion of the seal ring structure forms an obtuse angle with the first portion. The method further includes forming a first pad which is electrically coupled with the seal ring structure. The method further includes disposing a leakage current test structure in an area enclosed by the seal ring where at least one portion of the leakage current test structure is substantially parallel with the tilted portion of the seal ring structure. The method further includes forming a second pad which is electrically coupled with the leakage current test structure.Type: GrantFiled: July 2, 2014Date of Patent: June 23, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Ying Yang, Hsien-Wei Chen
-
Patent number: 8957503Abstract: A package includes a semiconductor device including an active surface having a contact pad. A redistribution layer (RDL) structure includes a first post-passivation interconnection (PPI) line electrically connected to the contact pad and extending on the active surface of the semiconductor device. An under-bump metallurgy (UBM) layer is formed over and electrically connected to the first PPI line. A seal ring structure extends around the upper periphery of the semiconductor device. The seal ring structure includes a seal layer extending on the same level as at least one of the first PPI line and the UBM layer.Type: GrantFiled: December 9, 2013Date of Patent: February 17, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ying Yang, Hsien-Wei Chen, Tsung-Yuan Yu, Shih-Wei Liang
-
Publication number: 20140315383Abstract: A method of making an integrated circuit including forming a seal ring structure around a circuit where the seal ring structure has a first portion and a tilted portion. The first portion of the seal ring structure is substantially parallel with an edge of the circuit. The tilted portion of the seal ring structure forms an obtuse angle with the first portion. The method further includes forming a first pad which is electrically coupled with the seal ring structure. The method further includes disposing a leakage current test structure in an area enclosed by the seal ring where at least one portion of the leakage current test structure is substantially parallel with the tilted portion of the seal ring structure. The method further includes forming a second pad which is electrically coupled with the leakage current test structure.Type: ApplicationFiled: July 2, 2014Publication date: October 23, 2014Inventors: Chung-Ying YANG, Hsien-Wei CHEN
-
Patent number: 8796686Abstract: An integrated circuit includes a seal ring structure disposed around a circuit that is disposed over a substrate. A first pad is electrically coupled with the seal ring structure. A leakage current test structure is disposed adjacent to the seal ring structure. A second pad electrically coupled with the leakage current test structure, wherein the leakage current test structure is configured to provide a leakage current test between the seal ring structure and the leakage current test structure.Type: GrantFiled: August 26, 2011Date of Patent: August 5, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ying Yang, Hsien-Wei Chen
-
Publication number: 20140091437Abstract: A package includes a semiconductor device including an active surface having a contact pad. A redistribution layer (RDL) structure includes a first post-passivation interconnection (PPI) line electrically connected to the contact pad and extending on the active surface of the semiconductor device. An under-bump metallurgy (UBM) layer is formed over and electrically connected to the first PPI line. A seal ring structure extends around the upper periphery of the semiconductor device. The seal ring structure includes a seal layer extending on the same level as at least one of the first PPI line and the UBM layer.Type: ApplicationFiled: December 9, 2013Publication date: April 3, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ying YANG, Hsien-Wei CHEN, Tsung-Yuan YU, Shih-Wei LIANG
-
Patent number: 8669651Abstract: A device includes a package substrate including a first non-reflowable metal bump extending over a top surface of the package substrate; a die over and bonded to the package substrate; and a package component over the die and bonded to the package substrate. The package component includes a second non-reflowable metal bump extending below a bottom surface of the package component. The package component is selected from the group consisting essentially of a device die, an additional package substrate, and combinations thereof. A solder bump bonds the first non-reflowable metal bump to the second non-reflowable metal bump.Type: GrantFiled: July 26, 2010Date of Patent: March 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ying Yang, Chao-Wen Shih, Hao-Yi Tsai, Hsien-Wei Chen, Mirng-Ji Lii, Tzuan-Horng Liu
-
Patent number: 8624359Abstract: A wafer level chip scale package (WLCSP) includes a semiconductor device including an active surface having a contact pad, and side surfaces. A mold covers the side surfaces of the semiconductor device. A RDL structure includes a first PPI line electrically connected to the contact pad and extending on the active surface of the semiconductor device. A UBM layer is formed over and electrically connected to the first PPI line. A seal ring structure extends around the upper periphery of the semiconductor device on the mold. The seal ring structure includes a seal layer extending on the same level as at least one of the first PPI line and the UBM layer. A method of manufacturing a WLCSP includes forming a re-routing laminated structure by simultaneously forming an interconnection line and a seal layer on the molded semiconductor devices.Type: GrantFiled: October 5, 2011Date of Patent: January 7, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ying Yang, Hsien-Wei Chen, Tsung-Yuan Yu, Shih-Wei Liang
-
Publication number: 20130270710Abstract: A customized seal ring for a semiconductor device is formed of multiple seal ring cells that are selected and arranged to produce a seal ring design. The cells include first cells that are coupled to ground and second cells that are not coupled to ground. The second cells that are not coupled to ground, include a higher density of metal features in an inner portion thereof, than the first seal ring cells. Dummy metal vias and other metal features that may be present in the inner portion of the second seal ring cells are absent from the inner portion of the first seal ring cells that are coupled to ground. The seal ring design may include various arrangements, including alternating and repeating sequences of the different seal ring cells.Type: ApplicationFiled: April 12, 2012Publication date: October 17, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsien-Wei CHEN, Chung-Ying YANG
-
Publication number: 20130270686Abstract: Apparatus and methods for forming a heat spreader on a substrate to release heat for a semi-conductor package are disclosed. The apparatus comprises a substrate. A dielectric layer is formed next to the substrate and in contact with a surface of the substrate. A heat spreader is formed next to the substrate and in contact with another surface of the substrate. A passivation layer is formed next to the dielectric layer. A connection pad is placed on top of the passivation layer. The substrate may comprise additional through-silicon-vias. The contact surface between the substrate and the heat spreader may be a scraggy surface. The packaging method further proceeds to connect a chip to the connection pad by way of a connection device such as a solder ball or a bump.Type: ApplicationFiled: April 11, 2012Publication date: October 17, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Wei Chen, Chung-Ying Yang, Chao-Wen Shih, Kai-Chiang Wu
-
Publication number: 20130087914Abstract: A wafer level chip scale package (WLCSP) includes a semiconductor device including an active surface having a contact pad, and side surfaces. A mold covers the side surfaces of the semiconductor device. A RDL structure includes a first PPI line electrically connected to the contact pad and extending on the active surface of the semiconductor device. A UBM layer is formed over and electrically connected to the first PPI line. A seal ring structure extends around the upper periphery of the semiconductor device on the mold. The seal ring structure includes a seal layer extending on the same level as at least one of the first PPI line and the UBM layer. A method of manufacturing a WLCSP includes forming a re-routing laminated structure by simultaneously forming an interconnection line and a seal layer on the molded semiconductor devices.Type: ApplicationFiled: October 5, 2011Publication date: April 11, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Ying YANG, Hsien-Wei CHEN, Tsung-Yuan YU, Shih-Wei LIANG