Patents by Inventor Chung-Yu Wang
Chung-Yu Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20140038360Abstract: Methods and apparatus for performing molding on die on wafer interposers. A method includes receiving an interposer assembly having a die side and an opposite side including two or more integrated circuit dies mounted on the die side of the interposer, the interposer assembly having spaces formed on the die side of the interposer between the two or more integrated circuit dies; mounting at least one stress relief feature on the die side of the interposer assembly in one of the spaces between the two or more integrated circuit dies; and molding the integrated circuit dies using a mold compound, the mold compound surrounding the two or more integrated circuit dies and the at least one stress relief feature. An apparatus is disclosed having integrated circuits mounted on a die side of an interposer, stress relief features between the integrated circuits and mold compound over the integrated circuits.Type: ApplicationFiled: October 16, 2013Publication date: February 6, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung Yu Wang, Chih-Wei Wu, Szu Wei Lu, Jing-Cheng Lin
-
Patent number: 8642390Abstract: Organic-adhesive tapes are often used to secure and protect the bumps during wafer processing after bump formation. While residual organic-adhesive tape may remain on the wafer after tape de-lamination, applying a bump template layer on the bumps before laminating the tape allows any residue to be removed afterwards and results in a residue-free wafer.Type: GrantFiled: March 17, 2010Date of Patent: February 4, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung Yu Wang, Jiann-Jong Wang
-
Patent number: 8628984Abstract: A package system includes a substrate having at least one first thermally conductive structure through the substrate. At least one second thermally conductive structure is disposed over the at least one first thermally conductive structure. At least one light-emitting diode (LED) is disposed over the at least one second thermally conductive structure.Type: GrantFiled: February 15, 2013Date of Patent: January 14, 2014Assignee: TSMC Solid State Lighting Ltd.Inventor: Chung Yu Wang
-
Patent number: 8629043Abstract: A method includes performing a dicing on a composite wafer including a plurality of dies, wherein the composite wafer is bonded on a carrier when the step of dicing is performed. After the step of dicing, the composite wafer is mounted onto a tape. The carrier is then de-bonded from the composite wafer and the first tape.Type: GrantFiled: November 16, 2011Date of Patent: January 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung Yu Wang, Jui-Pin Hung, Chih-Hao Chen, Chun-Hsing Su, Yi-Chao Mao, Kung-Chen Yeh, Yi-Lin Tsai, Ying-Tz Hung, Chin-Fu Kao, Shih-Yi Syu, Chin-Chuan Chang, Hsien-Wen Liu, Long Hua Lee
-
Publication number: 20130299984Abstract: Protection of a solder ball joint is disclosed in which the solder ball joint is located below the surface level of the encapsulating buffer layer. The buffering layer is etched to expose one or more electrode posts, each of which may be made up of a single column or multiple columns. A top layer resulting either from a top conductive cap or a plating layer around the electrode posts also lies below the buffer layer. When the solder ball is placed onto the posts, the solder/ball joint is protected in a position below the surface of the buffer layer, while still maintaining an electrical connection between the various solder balls and their associated or capping/plating material, electrode posts, wiring layers, and circuit layers. Therefore, the entire ball joint is protected from direct stress.Type: ApplicationFiled: July 19, 2013Publication date: November 14, 2013Inventors: Chung Yu Wang, Chien-Hsun Lee, Pei-Haw Tsao, Kuo-Chin Chang, Chung-Yi Lin, Bill Kiang
-
Publication number: 20130299855Abstract: An optical emitter is fabricated by bonding a Light-Emitting Diode (LED) die to a package wafer, electrically connecting the LED die and the package wafer, forming a phosphor coating over the LED die on the package wafer, molding a lens over the LED die on the package wafer, molding a reflector on the package wafer, and dicing the wafer into at least one optical emitter.Type: ApplicationFiled: July 15, 2013Publication date: November 14, 2013Inventors: Hao-Wei Ku, Chung Yu Wang, Yu-Sheng Tang, Hain-Hung Chen, Hao-Yu Yang, Ching-Yi Chen, Hsiao-Wen Lee, Chi Xiang Tseng, Sheng-Shin Guo, Tien-Ming Lin, Shang-Yu Tsai
-
Patent number: 8580683Abstract: Methods and apparatus for performing molding on die on wafer interposers. A method includes receiving an interposer assembly having a die side and an opposite side including two or more integrated circuit dies mounted on the die side of the interposer, the interposer assembly having spaces formed on the die side of the interposer between the two or more integrated circuit dies; mounting at least one stress relief feature on the die side of the interposer assembly in one of the spaces between the two or more integrated circuit dies; and molding the integrated circuit dies using a mold compound, the mold compound surrounding the two or more integrated circuit dies and the at least one stress relief feature. An apparatus is disclosed having integrated circuits mounted on a die side of an interposer, stress relief features between the integrated circuits and mold compound over the integrated circuits.Type: GrantFiled: September 27, 2011Date of Patent: November 12, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung Yu Wang, Chih-Wei Wu, Szu Wei Lu, Jing-Cheng Lin
-
Publication number: 20130285241Abstract: Apparatus for performing dicing of die on wafer interposers. Apparatuses are disclosed for use with the methods of dicing an interposer having integrated circuit dies mounted thereon. An apparatus includes a wafer carrier mounted in a frame and having a size corresponding to a silicon interposer, a fixture mounted to the wafer carrier and comprising a layer of material to provide mechanical support to the die side of the silicon interposer, the fixture being patterned to fill spaces between integrated circuit dies mounted on an interposer; and an adhesive tape disposed on a surface of the fixture for adhering to the surface of a silicon interposer. Additional alternative apparatuses are disclosed.Type: ApplicationFiled: June 25, 2013Publication date: October 31, 2013Inventors: Chung Yu Wang, Kung-Chen Yeh, Chih-Wei Wu, Szu Wei Lu, Jing-Cheng Lin
-
Publication number: 20130217188Abstract: A device includes a package component, and a die over and bonded to the package component. The die includes a substrate. A heat sink is disposed over and bonded to a back surface of the substrate through direct bonding.Type: ApplicationFiled: February 16, 2012Publication date: August 22, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung Yu Wang, Shih-Yi Syu, Jing-Cheng Lin
-
Patent number: 8501590Abstract: Methods and apparatus for performing dicing of die on wafer interposers. Methods are disclosed that include receiving an interposer assembly including one or more integrated circuit dies mounted on a die side of an interposer substrate and having scribe areas defined in spaces between the integrated circuit dies, the interposer having an opposite side for receiving external connectors; mounting the die side of the interposer assembly to a tape assembly, the tape assembly comprising an adhesive tape and preformed spacers disposed between and filling gaps between the integrated circuit dies; and sawing the interposer assembly by cutting the opposite side of the interposer in the scribe areas to make cuts through the interposer, the cuts separating the interposer into one or more die on wafer assemblies. Apparatuses are disclosed for use with the methods.Type: GrantFiled: July 5, 2011Date of Patent: August 6, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung Yu Wang, Kung-Chen Yeh, Chih-Wei Wu, Szu Wei Lu, Jing-Cheng Lin
-
Patent number: 8492263Abstract: Protection of a solder ball joint is disclosed in which the solder ball joint is located below the surface level of the encapsulating buffer layer. The buffering layer is etched to expose one or more electrode posts, each of which may be made up of a single column or multiple columns. A top layer resulting either from a top conductive cap or a plating layer around the electrode posts also lies below the buffer layer. When the solder ball is placed onto the posts, the solder/ball joint is protected in a position below the surface of the buffer layer, while still maintaining an electrical connection between the various solder balls and their associated or capping/plating material, electrode posts, wiring layers, and circuit layers. Therefore, the entire ball joint is protected from direct stress.Type: GrantFiled: November 16, 2007Date of Patent: July 23, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung Yu Wang, Chien-Hsiun Lee, Pei-Haw Tsao, Kuo-Chin Chang, Chung-Yi Lin, Bill Kiang
-
Patent number: 8486724Abstract: An optical emitter is fabricated by bonding a Light-Emitting Diode (LED) die to a package wafer, electrically connecting the LED die and the package wafer, forming a phosphor coating over the LED die on the package wafer, molding a lens over the LED die on the package wafer, molding a reflector on the package wafer, and dicing the wafer into at least one optical emitter.Type: GrantFiled: October 22, 2010Date of Patent: July 16, 2013Assignee: TSMC Solid State Lighting Ltd.Inventors: Hao-Wei Ku, Chung Yu Wang, Yu-Sheng Tang, Hsin-Hung Chen, Hao-Yu Yang, Ching-Yi Chen, Hsiao-Wen Lee, Chi Xiang Tseng, Sheng-Shin Guo, Tien-Ming Lin, Shang-Yu Tsai
-
Publication number: 20130119533Abstract: A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package.Type: ApplicationFiled: November 16, 2011Publication date: May 16, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Chen, Long Hua Lee, Chun-Hsing Su, Yi-Lin Tsai, Kung-Chen Yeh, Chung Yu Wang, Jui-Pin Hung, Jing-Cheng Lin
-
Publication number: 20130122689Abstract: A method includes performing a dicing on a composite wafer including a plurality of dies, wherein the composite wafer is bonded on a carrier when the step of dicing is performed. After the step of dicing, the composite wafer is mounted onto a tape. The carrier is then de-bonded from the composite wafer and the first tape.Type: ApplicationFiled: November 16, 2011Publication date: May 16, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung Yu Wang, Jui-Pin Hung, Chih-Hao Chen, Chun-Hsing Su, Yi-Chao Mao, Kung-Chen Yeh, Yi-Lin Tsai, Ying-Tz Hung, Chin-Fu Kao, Shih-Yi Syu, Chin-Chuan Chang, Hsien-Wen Liu, Long Hua Lee
-
Patent number: 8408734Abstract: A structure of lighting device includes a hood, a heat dissipater, at least one substrate board, and a fastener. The hood forms a receiving space, at least one fitting slot, and at least one heat dissipation opening. The fitting slot is located inside the receiving space. The heat dissipation opening is defined in a circumferential surface of the hood. The heat dissipater is received in the receiving space. The heat dissipater forms at least one guide section. The guide section opposes the fitting slot and is received in the fitting slot. The substrate board is electrically connected to at least one light-emitting diode. The substrate board is coupled to the heat dissipater. The heat dissipation opening allows for air circulation for removing heat generated by light-emitting diodes. Further, the heat dissipation opening is formed to have a width W less than 3 mm, and the heat dissipater is arranged to be spaced from a circumferential surface of the hood by a distance greater than 6 mm.Type: GrantFiled: June 22, 2010Date of Patent: April 2, 2013Assignee: Unity Opto Technology Co., Ltd.Inventors: Chih-Hsien Wu, Meng-Chieh Chou, Chung-Yu Wang
-
Publication number: 20130075937Abstract: Methods and apparatus for performing molding on die on wafer interposers. A method includes receiving an interposer assembly having a die side and an opposite side including two or more integrated circuit dies mounted on the die side of the interposer, the interposer assembly having spaces formed on the die side of the interposer between the two or more integrated circuit dies; mounting at least one stress relief feature on the die side of the interposer assembly in one of the spaces between the two or more integrated circuit dies; and molding the integrated circuit dies using a mold compound, the mold compound surrounding the two or more integrated circuit dies and the at least one stress relief feature. An apparatus is disclosed having integrated circuits mounted on a die side of an interposer, stress relief features between the integrated circuits and mold compound over the integrated circuits.Type: ApplicationFiled: September 27, 2011Publication date: March 28, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung Yu Wang, Chih-Wei Wu, Szu Wei Lu, Jing-Cheng Lin
-
Patent number: 8399269Abstract: A light-emitting device (LED) package component includes an LED chip having a first active bond pad and a second active bond pad. A carrier chip is bonded onto the LED chip through flip-chip bonding. The carrier chip includes a first active through-substrate via (TSV) and a second active TSV connected to the first and the second active bond pads, respectively. The carrier chip further includes a dummy TSV therein, which is electrically coupled to the first active bond pad, and is configured not to conduct any current when a current flows through the LED chip.Type: GrantFiled: May 17, 2012Date of Patent: March 19, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chung-Yu Wang
-
Patent number: 8390009Abstract: A package system includes a substrate having at least one first thermally conductive structure through the substrate. At least one second thermally conductive structure is disposed over the at least one first thermally conductive structure. At least one light-emitting diode (LED) is disposed over the at least one second thermally conductive structure.Type: GrantFiled: February 16, 2010Date of Patent: March 5, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chung Yu Wang
-
Publication number: 20130009316Abstract: Methods and apparatus for performing dicing of die on wafer interposers. Methods are disclosed that include receiving an interposer assembly including one or more integrated circuit dies mounted on a die side of an interposer substrate and having scribe areas defined in spaces between the integrated circuit dies, the interposer having an opposite side for receiving external connectors; mounting the die side of the interposer assembly to a tape assembly, the tape assembly comprising an adhesive tape and preformed spacers disposed between and filling gaps between the integrated circuit dies; and sawing the interposer assembly by cutting the opposite side of the interposer in the scribe areas to make cuts through the interposer, the cuts separating the interposer into one or more die on wafer assemblies. Apparatuses are disclosed for use with the methods.Type: ApplicationFiled: July 5, 2011Publication date: January 10, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung Yu Wang, Kung-Chen Yeh, Chih-Wei Wu, Szu Wei Lu, Jing-Cheng Lin
-
Publication number: 20120225509Abstract: A light-emitting device (LED) package component includes an LED chip having a first active bond pad and a second active bond pad. A carrier chip is bonded onto the LED chip through flip-chip bonding. The carrier chip includes a first active through-substrate via (TSV) and a second active TSV connected to the first and the second active bond pads, respectively. The carrier chip further includes a dummy TSV therein, which is electrically coupled to the first active bond pad, and is configured not to conduct any current when a current flows through the LED chip.Type: ApplicationFiled: May 17, 2012Publication date: September 6, 2012Applicant: TSMC Solid State Lighting Ltd.Inventor: Chung Yu Wang