Patents by Inventor Chung-Yu Wang
Chung-Yu Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120204951Abstract: A phosphor-contained solar cell comprises a photoelectric conversion layer for conversing the photo energy to electrical energy; a phosphor layer, disposed on at least one side of the photoelectric conversion layer, for improving the photoelectric conversion efficiency; the phosphor is up conversion phosphor or down conversion phosphor; wherein the up conversion phosphor is selected from X2Mo2O9:X or X2Mo2O9:X,X; the down-conversion phosphor is selected from JQX(PO4)2:X3+ or JQX(PO4)2:X2+,X2+; wherein X represents anyone of rare earth metal, J represents lithium, sodium or potassium, Q represents anyone of alkaline earth metal.Type: ApplicationFiled: November 22, 2011Publication date: August 16, 2012Inventors: Chung-Yu WANG, Yi-Fang CHEN
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Patent number: 8183579Abstract: A light-emitting device (LED) package component includes an LED chip having a first active bond pad and a second active bond pad. A carrier chip is bonded onto the LED chip through flip-chip bonding. The carrier chip includes a first active through-substrate via (TSV) and a second active TSV connected to the first and the second active bond pads, respectively. The carrier chip further includes a dummy TSV therein, which is electrically coupled to the first active bond pad, and is configured not to conduct any current when a current flows through the LED chip.Type: GrantFiled: March 2, 2010Date of Patent: May 22, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chung Yu Wang
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Patent number: 8183580Abstract: A light-emitting device (LED) package component includes an LED chip and a carrier chip. The carrier chip includes a first bond pad and a second bond pad on a surface of the carrier chip and bonded onto the LED chip through flip-chip bonding, and a third bond pad and a fourth bond pad on the surface of the carrier chip and electrically connected to the first bond pad and the second bond pad, respectively. The first bond pad and the second bond pad are on a same side of the carrier chip facing the LED chip. The carrier chip further includes at least one through substrate via (TSV) connected to the first and second bond pads.Type: GrantFiled: March 2, 2010Date of Patent: May 22, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chung Yu Wang
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Patent number: 8183578Abstract: A light-emitting device (LED) package component includes an LED chip and a carrier chip. The carrier chip includes a first and a second bond pad on a surface of the carrier chip; and a third and a fourth bond pad on the surface of the carrier chip and electrically connected to the first and the second bond pads, respectively. The first, the second, the third, and the fourth bond pads are on a same surface of the carrier chip. The LED package component further includes a first and a second metal bump bonding the first and the second bond pads, respectively, onto the LED chip through flip-chip bonding; and a window-type module substrate bonded onto the third and the fourth bond pads through flip-chip bonding. The window-type module substrate includes a window, with the LED chip configured to emit light toward the window.Type: GrantFiled: March 2, 2010Date of Patent: May 22, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chung Yu Wang
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Publication number: 20120097986Abstract: An optical emitter is fabricated by bonding a Light-Emitting Diode (LED) die to a package wafer, electrically connecting the LED die and the package wafer, forming a phosphor coating over the LED die on the package wafer, molding a lens over the LED die on the package wafer, molding a reflector on the package wafer, and dicing the wafer into at least one optical emitter.Type: ApplicationFiled: October 22, 2010Publication date: April 26, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hao-Wei KU, Chung Yu WANG, Yu-Sheng Tang, Hsin-Hung Chen, Hao-Yu Yang, Ching-Yi Chen, Hsiao-Wen Lee, Chi Xiang Tseng, Sheng-Shin Guo, Tien-Ming Lin, Shang-Yu Tsai
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Publication number: 20110317409Abstract: A structure of lighting device includes a heat dissipater having opposite edges respectively forming a guide slot and a groove. A substrate board has an edge received and retained in the guide slot and an opposite edge forming a mounting hole. A fastener is received through the mounting hole to tightly engage the groove so as to fix the substrate board to the heat dissipater. No pre-machining of thread tapping is needed to form inner-threaded holes first. The structure of lighting device offers advantages in respect of simple structural arrangement, efficient manufacturing and production, reduced labor and material used, and lowering of costs.Type: ApplicationFiled: June 23, 2010Publication date: December 29, 2011Applicant: Unity Opto Technology Co., Ltd.Inventors: Chih-Hsien Wu, Chung-Yu Wang, Meng-Chieh Chou
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Publication number: 20110292646Abstract: A structure of lighting device includes g a hood, a heat dissipater, at least one substrate board, and a fastener. The hood forms a receiving space, at least one fitting slot, and at least one heat dissipation opening. The fitting slot is located inside the receiving space. The heat dissipation opening is defined in a circumferential surface of the hood. The heat dissipater is received in the receiving space. The heat dissipater forms at least one guide section. The guide section opposes the fitting slot and is received in the fitting slot. The substrate board is electrically connected to at least one light-emitting diode. The substrate board is coupled to the heat dissipater. The heat dissipation opening allows for air circulation for removing heat generated by light-emitting diodes. Further, the heat dissipation opening is formed to have a width W less than 3mm, and the heat dissipater is arranged to be spaced from a circumferential surface of the hood by a distance greater than 6mm.Type: ApplicationFiled: June 22, 2010Publication date: December 1, 2011Applicant: Unity Opto Technology Co., Ltd.Inventors: Chih-Hsien Wu, Meng-Chieh Chou, Chung-Yu Wang
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Patent number: 8046106Abstract: A controlling method and a controlling system for saving energy of a building are provided. In the present method, a user environment requirement is obtained first. Then, a plurality of cover ratios of a sunshade device on an opening of a building is defined, and according to an environment parameter and the user environment requirement, a total electricity consumption required by air conditioning equipment and by lighting equipment in the building corresponding to each of the cover ratios is calculated. Finally, a cover ratio that produces the minimum total electricity consumption is obtained, and the sunshade device, the air conditioning equipment and the lighting equipment are adjusted according to the obtained cover ratio, so as to make the building meet the user environment requirement and maintain a status of the minimum total energy consumption.Type: GrantFiled: December 16, 2008Date of Patent: October 25, 2011Assignee: Institute for Information IndustryInventors: Kun-Cheng Tsai, Chung-Yu Wang, Jing-Tian Sung
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Publication number: 20110230043Abstract: Organic-adhesive tapes are often used to secure and protect the bumps during wafer processing after bump formation. While residual organic-adhesive tape may remain on the wafer after tape de-lamination, applying a bump template layer on the bumps before laminating the tape allows any residue to be removed afterwards and results in a residue-free wafer.Type: ApplicationFiled: March 17, 2010Publication date: September 22, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung Yu WANG, Jiann-Jong WANG
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Publication number: 20110215361Abstract: A light-emitting device (LED) package component includes an LED chip and a carrier chip. The carrier chip includes a first bond pad and a second bond pad on a surface of the carrier chip and bonded onto the LED chip through flip-chip bonding, and a third bond pad and a fourth bond pad on the surface of the carrier chip and electrically connected to the first bond pad and the second bond pad, respectively. The first bond pad and the second bond pad are on a same side of the carrier chip facing the LED chip. The carrier chip further includes at least one through substrate via (TSV) connected to the first and second bond pads.Type: ApplicationFiled: March 2, 2010Publication date: September 8, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chung Yu Wang
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Publication number: 20110215360Abstract: A light-emitting device (LED) package component includes an LED chip having a first active bond pad and a second active bond pad. A carrier chip is bonded onto the LED chip through flip-chip bonding. The carrier chip includes a first active through-substrate via (TSV) and a second active TSV connected to the first and the second active bond pads, respectively. The carrier chip further includes a dummy TSV therein, which is electrically coupled to the first active bond pad, and is configured not to conduct any current when a current flows through the LED chip.Type: ApplicationFiled: March 2, 2010Publication date: September 8, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chung Yu Wang
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Publication number: 20110215354Abstract: A light-emitting device (LED) package component includes an LED chip and a carrier chip. The carrier chip includes a first and a second bond pad on a surface of the carrier chip; and a third and a fourth bond pad on the surface of the carrier chip and electrically connected to the first and the second bond pads, respectively. The first, the second, the third, and the fourth bond pads are on a same surface of the carrier chip. The LED package component further includes a first and a second metal bump bonding the first and the second bond pads, respectively, onto the LED chip through flip-chip bonding; and a window-type module substrate bonded onto the third and the fourth bond pads through flip-chip bonding. The window-type module substrate includes a window, with the LED chip configured to emit light toward the window.Type: ApplicationFiled: March 2, 2010Publication date: September 8, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chung Yu Wang
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Publication number: 20110198638Abstract: A package system includes a substrate having at least one first thermally conductive structure through the substrate. At least one second thermally conductive structure is disposed over the at least one first thermally conductive structure. At least one light-emitting diode (LED) is disposed over the at least one second thermally conductive structure.Type: ApplicationFiled: February 16, 2010Publication date: August 18, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Chung Yu WANG
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Publication number: 20110193056Abstract: A method of forming a light-emitting device (LED) package component includes providing a substrate; forming an LED on the substrate; and lifting the LED off the substrate. A carrier wafer is provided, which includes a through-substrate via (TSV) configured to electrically connecting features on opposite sides of the carrier wafer. The LED is bonded onto the carrier wafer, with the LED electrically connected to the TSV.Type: ApplicationFiled: February 11, 2010Publication date: August 11, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chung Yu Wang
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Patent number: 7833896Abstract: A method of manufacturing a semiconductor device and structure thereof. The method includes providing a workpiece, the workpiece having at least one conductive pad partially exposed through an opening in a passivation layer, the passivation layer having a top surface and the opening in the passivation layer having sidewalls. A barrier layer is formed over the at least one conductive pad, wherein the barrier layer lines the sidewalls of the opening in the passivation layer and is disposed over a top portion of the passivation layer proximate the opening. A conductive cap is formed over the barrier layer within the opening in the passivation layer, and the conductive cap is recessed to a height below the top surface of the passivation layer. The conductive cap may be used for testing with a probe or may be used for wire-bonding.Type: GrantFiled: September 23, 2004Date of Patent: November 16, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung Yu Wang, Chien-Hsiun Lee
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Publication number: 20100131110Abstract: A controlling method and a controlling system for saving energy of a building are provided. In the present method, a user environment requirement is obtained first. Then, a plurality of cover ratios of a sunshade device on an opening of a building is defined, and according to an environment parameter and the user environment requirement, a total electricity consumption required by air conditioning equipment and by lighting equipment in the building corresponding to each of the cover ratios is calculated. Finally, a cover ratio that produces the minimum total electricity consumption is obtained, and the sunshade device, the air conditioning equipment and the lighting equipment are adjusted according to the obtained cover ratio, so as to make the building meet the user environment requirement and maintain a status of the minimum total energy consumption.Type: ApplicationFiled: December 16, 2008Publication date: May 27, 2010Applicant: INSTITUTE FOR INFORMATION INDUSTRYInventors: Kun-Cheng Tsai, Chung-Yu Wang, Jing-Tian Sung
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Patent number: 7662665Abstract: A method for fabricating a semiconductor package is provided. In one embodiment, a semiconductor chip having a plurality of exposed conductive layers thereon is provided. A first substrate having a first surface and a second surface is provided, the first surface having a plurality of exposed via plugs thereunder. The semiconductor chip is bonded to the first substrate, wherein the plurality of exposed conductor layers are aligned and in contact with the surfaces of the exposed via plugs. A portion of the second surface of the first substrate is then removed to expose the opposite ends of the plurality of via plugs. A plurality of UBM layers is formed on the surfaces of the opposite ends of the plurality of via plugs. A plurality of solder bumps is formed and mounted on the UBM layers. A second substrate having a first surface and a second surface is provided, the solder bumps being mounted to the first surface of the second substrate.Type: GrantFiled: January 22, 2007Date of Patent: February 16, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Shien Chen, Kuo-Chin Chang, Szu-Wei Lu, Pei-Haw Tsao, Chung-Yu Wang, Han-Liang Tseng, Mirng-Ji Lii
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Publication number: 20090130840Abstract: Protection of a solder ball joint is disclosed in which the solder ball joint is located below the surface level of the encapsulating buffer layer. The buffering layer is etched to expose one or more electrode posts, each of which may be made up of a single column or multiple columns. A top layer resulting either from a top conductive cap or a plating layer around the electrode posts also lies below the buffer layer. When the solder ball is placed onto the posts, the solder/ball joint is protected in a position below the surface of the buffer layer, while still maintaining an electrical connection between the various solder balls and their associated or capping/plating material, electrode posts, wiring layers, and circuit layers. Therefore, the entire ball joint is protected from direct stress.Type: ApplicationFiled: November 16, 2007Publication date: May 21, 2009Inventors: Chung Yu Wang, Chien-Hsiun Lee, Pei-Haw Tsao, Kuo-Chin Chang, Chung-Yi Lin, Bill Kiang
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Patent number: 7446398Abstract: A bump pattern design for flip chip semiconductor packages includes a pattern of contact pads formed on a package substrate. Each contact pad is adapted to receive a corresponding solder bump from a semiconductor chip attached thereto. The pattern includes a central portion and a peripheral portion with a transition portion therebetween. The transition portion has a lower pattern density than the central portion and peripheral portions. In the peripheral portion is at least one outer portion having a pattern density less than the average pattern density of the central portion. The outer portions of reduced pattern density may be the corner sections in a rectangular bump pattern and may further include channels that are void of contact pads. The peripheral portion may include an average pitch between most of the rows and columns, but also an increased pitch between some adjacent rows and columns.Type: GrantFiled: August 1, 2006Date of Patent: November 4, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pao-Kang Niu, Pei-Haw Tsao, Hao-Yi Tsai, Yung-Kuan Hsiao, Chung Yu Wang, Shang-Yun Hou, Lin Yu-Ting
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Patent number: 7443010Abstract: A matrix form semiconductor package substrate that has an electrode situated in-between a plurality of IC package substrates for providing electrical communication to conductive pads on the substrate is provided. The matrix form semiconductor package substrate includes a plurality of IC package substrates that are integrally formed on a strip in a matrix pattern that has a boundary between each two of the plurality of IC package substrates. Each of the plurality of IC package substrates has a multiplicity of conductive pad traces and an electrode, or a plating bar, formed in a serpentine configuration along the boundary for providing electrical communication to the multiplicity of conductive pads.Type: GrantFiled: April 5, 2001Date of Patent: October 28, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pei-Haw Tsao, Chender Huang, Chung-Yu Wang