Abstract: An optical mouse chip with silicon retina structure comprises an image sensor array, an accumulator and a comparing/selecting unit. The image sensor array senses a direction parameter of an image along each axis. The accumulator sums the direction parameters of the image along different axes. The comparing/selecting unit selects a largest one from the sum of direction parameters of the image along different axes to determine a moving direction of the image.

Abstract: Dispersion is measured for an end-to-end link using two carrier wavelengths with a phase-synchronized signal modulated on each, and a single receiver that detects the BER of the combined fields. The power ratio of the two fields is chosen such that the weaker field modulates the eye of the stronger field, leading to slight periodic eye closure BER(&tgr;)≅BER(&tgr;+TB) whenever the relative group delay changes by the bit period TB. The magnitude of the relative group delay can therefore be inferred from the undulated BER response as a function of the wavelength detuning. A fit function is selected for the group delay response and the dispersion parameter D and dispersion slope S are calculated from this fit function after the function parameters are determined.

Abstract: An optical mouse chip with silicon retina structure comprises an image sensor array, an accumulator and a comparing/selecting unit. The image sensor array senses a direction parameter of an image along each axis. The accumulator sums the direction parameters of the image along different axes. The comparing/selecting unit selects a largest one from the sum of direction parameters of the image along different axes to determine a moving direction of the image.

Abstract: A method of equalizing the channels of a WDM link comprises identifying an error threshold level BERFail for the BER defined for each signal S(j) in accordance with the channel rate, and determining the attenuation A(j) of, for example, the power P(j) of each signal S(j) transmitted over the WDM link. The transmitter powers are adjusted taking into account the attenuations determined for all channels. The attenuation A(j) for channel (j) is determined by first setting the power P(j) of all signals S(j) to a maximum PMax, attenuating the power P(j) of channel (j) until the BER reaches the threshold value BERFail, measuring the power corresponding to the BERFail for that channel, and calculating the difference between the PMax and P(j)Fail. The transmitter powers are then set according to the relationship P(j)=PMax−&eegr;(A(j)−AMin), where &eegr; is 0.8 for a system with 3-4 channels.

Abstract: A method of equalizing the channels of a WDM link comprises identifying an error threshold level BER.sub.Fail for the BER defined for each signal S(j) in accordance with the channel rate, and determining the attenuation A(j) of, for example, the power P(j) of each signal S(j) transmitted over the WDM link. The transmitter powers are adjusted taking into account the attenuations determined for all channels. The attenuation A(j) for channel (j) is determined by first setting the power P(j) of all signals S(j) to a maximum P.sub.Max, attenuating the power P(j) of channel (j) until the BER reaches the threshold value BER.sub.Fail, measuring the power corresponding to the BER.sub.Fail for that channel, and calculating the difference between the P.sub.Max and P(j).sub.Fail. The transmitter powers are then set according to the relationship P(j)=P.sub.Max -.eta.(A(j)-A.sub.Min), where .eta. is 0.8 for a system with 3-4 channels.

Abstract: A substrate-triggering ESD protection circuit is provided for use on a deep-submicron integrated circuit for ESD protection of the integrated circuit. The ESD protection circuit is incorporated between an input end and the internal circuit of the integrated circuit formed on a substrate. The ESD protection circuit utilizes a featured substrate-triggering operation to trigger the ESD-protection transistors formed in N-wells of the substrate into conducting state so as to bypass the ESD current to the ground. The ESD protection circuit allows a simplified semiconductor structure to fabricate, while nonetheless providing an increased level of ESD protection capability for the deep-submicron integrated circuit.

Abstract: An external adapter circuitry is plugged into the printer port of a host computer to provide the utility of computer telephony for the host computer. The circuitry is housed in a compact box which is about the size of a common parallel port connector. The circuitry consists of a telephone line interface for receiving and sending signals from/to the telephone line; a printer port interface for sending data to and receiving data from the host computer; a couple of registers for latching signal-in and signal-out; a A/D converter for converting analog signals to digital signals; and a D/A converter for converting digitized signals to analog signals. More specially, the electricity of the entire circuitry is supplied from a signal-to-power converter which obtains voltages from the printer port. Therefore, the external adapter circuitry does not need a power line for external power supply.

Abstract: A CMOS device containing a plurality of hexagon cells over a semiconductor substrate is disclosed. Each hexagon cell includes a hexagonal ring gate, a drain diffusion region and a source diffusion region. The hexagonal ring gate is made of conducting materials and a dielectric layer over the substrate, therefore defining a channel region in the substrate between the gate and the substrate. The entire drain diffusion region in the substrate is enclosed by the hexagonal ring gate. The source diffusion region surrounds the hexagonal ring gate in the substrate. Each hexagon cell further provides a drain contact in the center of the drain diffusion region. A plurality of source contacts are arranged around the ring gate over the substrate. The hexagon cells of a unique hexagon device are surrounded by a first guard ring and a second guard ring. The hexagon device can be used as a CMOS output buffer or input ESD protection circuit to reduce the layout area of an integrated circuit.

Abstract: The present invention is an electronic device, and more particularly an MOS transistor. A square-type layout style is used to realize the MOS device. By using the present layout style, the output driving/sinking capability of output buffers as well as the ESD protection capability of NMOS and PMOS devices in output buffers or input ESD protection circuits are significantly improved within smaller layout area. Both drain diffusion area and drain-to-bulk parasitic capacitance at the output node are reduced by this square-type layout. Devices using the present layout style can be assembled to form larger, rectangular (or square) and similarly functioning devices. Thus, the present square-type layout style is very attractive to submicron CMOS VLSI/ULSI in high-density and high-speed applications.

Abstract: The present invention is related to a capacitor-couple electrostatic discharge (ESD) protection circuit for protecting an internal circuit and/or an output buffer of an IC from being damaged by an ESD current. The capacitor-couple ESD protection circuit according to the present invention includes an ESD bypass device for bypassing the ESD current, a capacitor-couple circuit for coupling a portion of voltage to the ESD bypass device, and a potential leveling device for keeping an ESD voltage transmitted for the internal circuit at a low potential level. By using the present ESD protection circuit, the snapback breakdown voltage can be lowered to protect the very thin gate oxide of the internal circuit especially in the submicron CMOS technologies.

Abstract: A true type single-phase shift circuit including a pair of PMOS transistors, a pair of NMOS transistors, a pair of first-type MOS transistors and one second-type transistor. The source terminals of the two PMOS transistors are both coupled to a first electric potential, the gate terminal of one PMOS transistor is coupled to a data signal, and the gate terminal of the second PMOS transistor is connected between the two first-type MOS transistors. The source terminals of the two NMOS transistors are both coupled to a second electric potential; the gate terminal of one NMOS transitors is coupled to the data signal and the gate of the second NMOS transistor is connected between the two first-type MOS transistors. The two first type MOS transistors are serially connected between the drain terminals of one of the two PMOS transistors and the drain terminal of one of the two NMOS transistors. Each gate terminal of the two first type MOS transistors is coupled to a clock pulse signal.

Abstract: An electrostatic discharge (ESD) circuit for protecting a semiconductor integrated circuit (IC) device is disclosed. One ESD circuit is located between each I/O buffering pad that connects to one lead pin and the internal circuitry of IC. The ESD circuit is connected to both power terminals. The ESD circuit comprises first and second low-voltage-trigger SCRs (LVTSCRs), each having an anode, a cathode, an anode gate and a cathode gate. The anode and anode gate of the first SCR are connected to a first power terminal, the cathode of the first SCR is connected to its I/O buffering pad, and the cathode gate of the first SCR is connected to the second power terminal. The ESD circuit further comprises a PMOS transistor having drain, source, gate, and bulk terminals. The PMOS transistor's gate, source and bulk terminals are connected to the first power terminal, the PMOS transistor drain terminal is connected to the cathode gate of the first SCR.

Abstract: A complementary-SCR electrostatic discharge protection circuit in a silicon substrate, coupling to I/O pads for bypassing electrostatic current of positive or negative polarity respect to power supply voltages V.sub.DD and V.sub.SS. The circuit comprises a first SCR and a second SCR each having an anode, a cathode, an anode gate and a cathode gate. The circuit of the present invention preferably includes a finger type layout structure for providing a larger capacity to bypass electrostatic current. It is also characterized by a base-emitter shorting design to avoid a V.sub.DD -to-V.sub.SS latch-up effect.

Abstract: A CMOS dynamic logic structure has a plurality of logic gates, and the logic gates includes type-1 and type-3 logic gates alternately connected with each other. Each logic gate is separated into a function unit and a driver unit. The function unit has a PMOS precharge transistor, and a logic tree block stacked with the PMOS precharge transistor. The driver unit has an NMOS evaluation transistor, and the NMOS evaluation transistor and the PMOS precharge transistor of the previous-stage logic gate is controlled by an identical clock in order not to be turned on simultaneously.

Abstract: A sampled-data, current-mode circuit implements analog functions in a standard digital process. Among sampled-data current-mode circuits, the current S/H (CSH) circuit is a key component. This fully differential CSH circuit was implemented in a 1.2 .mu.m N-well double-poly double metal CMOS technology adapted to 8-bit resolution at a 15 MHz sampling rate.

Abstract: Precise CMOS bandgap voltage and current references which uses the difference of MOS source-gate voltages to perform efficient curvature compensation are proposed and analyzed. Applying the developed design strategies, bandgap voltage references (BVR) with a temperature drift below 10 ppm/.degree.C. and a power supply drift below 10 ppm/V can be realized. For bandgap current references, both drifts can be under 15 ppm. An experimental BVR chip shows an average drift of 5.5 ppm/.degree.C. from -60.degree. C. to 150.degree. C. and 25 .mu.V/V for supply voltages between 5 V and 15 V at 25.degree. C. Due to novel curvature compensation, the circuit structure of the proposed references is simple and both chip area and power consumption are small.

Abstract: A circuit for protecting a CMOS chip against damage from electrostatic discharges (ESD) has four SCRs connected between the line to be protected and the two power supply terminals, V.sub.DD and V.sub.SS. The SCRs are poled to conduct ESD current of either polarity to each power supply terminal. The bipolar transistors for the SCRs and the associated components are arranged in the chip in an advantageous way that reduces the input/output parasitic capacitance and improves the protection capability of this proposed circuit with a low ESD trigger-on voltage.

Abstract: A circuit for protecting a CMOS chip against damage from electrostatic discharges (ESD) has four SCRs connected between the line to be protected and the two power supply termiamls, V.sub.DD and V.sub.SS. The SCRs are poled to conduct ESD current of either polarity to each power supply terminal. The bipolar transistors for the SCRs and the associated component are arranged in the chip in an advantageous way that reduces the input/output parasitic capacitance and improves the protection capability of this proposed circuit with a low ESD trigger-on voltage.

Abstract: Backward-mapping switched capacitor (SC) differentiators for MOS technology integrated circuit implementation, as well as forward mapping (FM) and bilinear-mapping (BIM) SC differentiators, are disclosed. The SC differentiator is employed in filters either alone or in combination with SC integrators. The filters include biquads, ladder filters, FIR filters, IIR filters and N-path filters.A fully differential operational amplifier with high and symmetrical driving capability is also described.

Abstract: Sigma-delta analog to digital converters based upon switched capacitor delay and switched capacitor differentiator circuits are described. These switched capacitor circuits have the advantages that they are less sensitive to clock feed-through noise, dc offset voltage and power supply voltage, etc. Design examples of one-bit second-order sigma-delta analog digital converter are given to substantiate both design methodology, circuit features and the utility of these new circuit structures.