Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

Abstract: A method of using NC-MRA to generate pelvic veins images and measure rate of blood flow includes subjecting a lay patient to undergo magnetic resonance scan in cooperation with an ECG monitor and a respiration monitor; scanning coronary sections and transverse sections of kidney veins, lower cavity veins, common iliac veins, and external iliac veins to generate two-dimensional images wherein the two-dimensional images use balanced turbo field echo wave sequence; scanning coronary sections of common cardinal veins of abdominal cavity to generate three-dimensional images wherein the three-dimensional images use fast spin-echo short tau inversion recovery wave sequence and sample signals when the ECG monitor monitors myocardial contractility; and using quantification phase-contrast analysis to measure blood flowing through the transverse sections of the veins in a two-dimensional scan.

Abstract: A trim circuit for an e-fuse unit includes: a mirroring circuit for receiving an enable signal, when triggered by the enable signal, the mirroring circuit generating a driving voltage; and a driving transistor coupled to the mirroring circuit, in response to the driving voltage from the mirroring circuit, the driving transistor turning ON to generate a MOS current to an output node, wherein the output node is coupled to the e-fuse unit, and in response to the MOS current from the output node, the e-fuse unit is burned out.

Abstract: A trim circuit for an e-f use unit includes: a mirroring circuit for receiving an enable signal, when triggered by the enable signal, the mirroring circuit generating a driving voltage; and a driving transistor coupled to the mirroring circuit, in response to the driving voltage from the mirroring circuit, the driving transistor turning ON to generate a MOS current to an output node, wherein the output node is coupled to the e-fuse unit, and in response to the MOS current from the output node, the e-fuse unit is burned out.

Abstract: A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a first dielectric layer covering on the oxide-semiconductor layer and the source/drain regions, a second gate between the two source/drain regions and partially covering the oxide-semiconductor layer, and a charge storage structure between the first gate electrode and the oxide-semiconductor layer.

Abstract: A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a first dielectric layer covering on the oxide-semiconductor layer and the source/drain regions, a second gate between the two source/drain regions and partially covering the oxide-semiconductor layer, and a charge storage structure between the first gate electrode and the oxide-semiconductor layer.

Abstract: The present invention provides a semiconductor device including a semiconductor substrate, a first well, a second well, a gate electrode, an oxide semiconductor structure and a diode. The first well is disposed in the semiconductor substrate and has a first conductive type, and the second well is also disposed in the semiconductor substrate, adjacent to the first well, and has a second conductive type. The gate electrode is disposed on the first well. The oxide semiconductor structure is disposed on the semiconductor substrate and electrically connected to the second well. The diode is disposed between the first well and the second well.

Abstract: A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a dielectric layer, a first gate electrode, a second gate electrode and a charge storage structure. The oxide-semiconductor layer is disposed on the first gate electrode on the substrate. The source/drain regions are disposed on the oxide-semiconductor layer. The first dielectric layer covers on the oxide-semiconductor layer and source/drain regions. A second gate electrode is disposed between source/drain regions and partially covers the oxide-semiconductor layer. The oxide-semiconductor layer may be optionally disposed between the first gate electrode and the oxide-semiconductor layer or be disposed on the second gate electrode.

Abstract: A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a dielectric layer, a first gate electrode, a second gate electrode and a charge storage structure. The oxide-semiconductor layer is disposed on the first gate electrode on the substrate. The source/drain regions are disposed on the oxide-semiconductor layer. The first dielectric layer covers on the oxide-semiconductor layer and source/drain regions. A second gate electrode is disposed between source/drain regions and partially covers the oxide-semiconductor layer. The oxide-semiconductor layer may be optionally disposed between the first gate electrode and the oxide-semiconductor layer or be disposed on the second gate electrode.

Abstract: The present invention provides a semiconductor device including a semiconductor substrate, a first well, a second well, a gate electrode, an oxide semiconductor structure and a diode. The first well is disposed in the semiconductor substrate and has a first conductive type, and the second well is also disposed in the semiconductor substrate, adjacent to the first well, and has a second conductive type. The gate electrode is disposed on the first well. The oxide semiconductor structure is disposed on the semiconductor substrate and electrically connected to the second well. The diode is disposed between the first well and the second well.

Abstract: A mask set includes a first mask and a second mask. The first mask includes geometric patterns. The second mask includes at least a strip-shaped pattern with a first edge and a second edge opposite to the first edge. The strip-shaped pattern has a centerline along a long axis of the strip-shaped pattern. The first edge includes inwardly displaced segments shifting towards the centerline and each of the inwardly displaced segments overlaps each of the geometric patterns.

Abstract: A mask set includes a first mask and a second mask. The first mask includes geometric patterns. The second mask includes at least a strip-shaped pattern with a first edge and a second edge opposite to the first edge. The strip-shaped pattern has a centerline along a long axis of the strip-shaped pattern. The first edge includes inwardly displaced segments shifting towards the centerline and each of the inwardly displaced segments overlaps each of the geometric patterns.

Abstract: A semiconductor structure includes multiple buried gates which are disposed in a substrate and have a first source and a second source, an interlayer dielectric layer covering the multiple buried gates and the substrate as well as a core dual damascene plug including a first plug, a second plug and an insulating slot. The insulating slot is disposed between the first plug and the second plug so that the first plug and the second plug are mutually electrically insulated. The first plug and the second plug respectively penetrate the interlayer dielectric layer and are respectively electrically connected to the first source and the second source.

Abstract: A memory unit includes a substrate, at least one charge storage element, at least one first recessed access element, and an isolation portion. The substrate has a surface and the first recessed access element is disposed in an active area of the substrate and extending from the surface into the substrate. The first recessed access element is electrically connected to the charge storage element and induces in the substrate a first depletion region. The isolation portion is adjacent to the active area and extending from the surface into the substrate. The isolation portion includes a trenched isolating barrier and a second recessed access element. The second recessed access element is disposed in the trenched isolating barrier and induces in the substrate a second depletion region merging with the first depletion region.

Abstract: A semiconductor electronic device structure includes an active area array disposed in a substrate, an isolation structure, a plurality of recessed gate structures, a plurality of word lines, and a plurality of bit lines. The active area array a plurality of active area columns and a plurality of active area rows, defining an array of active areas. The substrate has two recesses formed at the central region thereof. Each recessed gate structure is respectively disposed in the recess. A protruding structure is formed on the substrate in each recess. A STI structure of the isolation structure is arranged between each pair of adjacent active area rows. Word lines are disposed in the substrate, each electrically connecting the gate structures there-under. Bit lines are disposed above the active areas, forming a crossing pattern with the word lines.

Abstract: A test key structure is provided. The test key structure comprises at least one semiconductor element. Each of the at least one semiconductor element including a well, a source region, a drain region and a gate. The source region is disposed in the well. The drain region is disposed in the well and separated from the source region. The gate is disposed above the well. The source region, the drain region and the well have the same type of doping.

Abstract: A PMOS field effect transistor includes a substrate, a first nitride layer, a mesa structure, two gate oxide films, a gate stack layer and a second nitride layer. The substrate has a oxide layer and a first doping area. The first nitride layer is located on the oxide layer. The mesa structure includes a first strained Si—Ge layer, an epitaxial Si layer and a second strained Si—Ge layer. The first strained Si—Ge layer is located on the oxide layer and the first nitride layer. The epitaxial Si layer is located on the first strained Si—Ge layer. The second strained Si—Ge layer is located on the epitaxial Si layer. In the surface layer of the second strained Si—Ge layer, there is a second doping area. The two gate oxide films are located at two sides of the mesa structure.

Abstract: A semiconductor having through-silicon via includes a substrate, an outer dielectric liner, an inner dielectric liner and a conductive contacting layer. The substrate has a top surface and a bottom surface and defining at least one through-silicon via going through the top surface toward the bottom surface. The outer dielectric liner covers the top surface of the substrate. The inner dielectric liner covers a wall of the through-silicon via. The thickness of the inner dielectric liner reduces from the top surface toward the bottom surface. The conductive contacting liner over fills the through-silicon via and is exposed on the top surface.

Abstract: A PMOS field effect transistor includes a substrate, a first nitride layer, a mesa structure, two gate oxide films, a gate stack layer and a second nitride layer. The substrate has a oxide layer and a first doping area. The first nitride layer is located on the oxide layer. The mesa structure includes a first strained Si—Ge layer, an epitaxial Si layer and a second strained Si—Ge layer. The first strained Si—Ge layer is located on the oxide layer and the first nitride layer. The epitaxial Si layer is located on the first strained Si—Ge layer. The second strained Si—Ge layer is located on the epitaxial Si layer. In the surface layer of the second strained Si—Ge layer, there is a second doping area. The two gate oxide films are located at two sides of the mesa structure.

Abstract: A memory unit includes a substrate, at least one charge storage element, at least one first recessed access element, and an isolation portion. The substrate has a surface and the first recessed access element is disposed in an active area of the substrate and extending from the surface into the substrate. The first recessed access element is electrically connected to the charge storage element and induces in the substrate a first depletion region. The isolation portion is adjacent to the active area and extending from the surface into the substrate. The isolation portion includes a trenched isolating barrier and a second recessed access element. The second recessed access element is disposed in the trenched isolating barrier and induces in the substrate a second depletion region merging with the first depletion region.