Abstract: A method for forming a recessed channel device includes providing a substrate with a plurality of trench capacitors formed therein, each of the trench capacitors including a plug protruding above the substrate; forming a spacer on each of the plugs; forming a plurality of trench isolations along a first direction in the substrate adjacent to the trench capacitors so as to define an active area exposing the substrate; removing a portion of the substrate by using the spacers and the trench isolations as a mask to form a recessed channel; and trimming the recessed channel so that a surface profile of the recessed channel presents a three-dimensional shape. A recessed channel device with a rounded channel profile is also provided.

Abstract: A checkerboard deep trench dynamic random access memory cell array layout is disclosed, which includes a substrate, a plurality of gate conductor lines disposed on the substrate, a plurality of checkerboard-arranged and staggered deep trench capacitor structures embedded in the substrate under the gate conductor lines, and a plurality of active areas formed in the substrate under the gate conductor lines, alternatively arranged with the deep trench capacitor structures, and electrically connected with an adjacent deep trench capacitor structure. The width of the parts of the gate conductor lines above the deep trench capacitor structures is narrower than that of the parts of the gate conductor lines above the active areas.

Abstract: A recessed-gate transistor device includes a gate electrode embedded in a gate trench formed in a semiconductor substrate, wherein the gate trench includes a vertical sidewall and a U-shaped bottom. A source region is provided at one side of the gate trench within the semiconductor substrate. A drain region is provided at the other side thereof. An asymmetric gate dielectric layer is formed between the gate electrode and the semiconductor substrate. The asymmetric gate dielectric layer has a first thickness between the gate electrode and the drain region and a second thickness between the gate electrode and the source region, wherein the first thickness is thicker than the second thickness.

Abstract: A DRAM structure has a substrate, a buried transistor with a fin structure, a trench capacitor, and a surface strap on the surface of the substrate. The surface strap is used to electrically connect a drain region to the trench capacitor.

Abstract: A method of fabricating self-aligned recess utilizing asymmetric poly spacer is disclosed. A semiconductor substrate having thereon a first pad layer and second pad layer is provided. A plurality of trenches is embedded in a memory array region of the semiconductor substrate. Each of the trenches includes a trench top layer that extrudes from a main surface of the semiconductor substrate. Asymmetric poly spacer is formed on one side of the extruding trench top layer and is used, after oxidized, as a mask for forming a recess in close proximity to the trenches.

Abstract: The present invention discloses a structure of a buried word line, which comprises a semiconductor substrate having a U-shape trench, a U-shape gate dielectric layer in the U-shape trench, a polysilicon layer on the U-shape gate dielectric layer, a conducting layer on the polysilicon layer, and a cover dielectric layer on the conducting layer. The semiconductor structure may have a minimized size and when recess channels are formed thereby, the integration is accordingly improved without suffering from the short channel effect.

Abstract: The present invention discloses a semiconductor structure comprising a semiconductor substrate having a U-shape trench, a U-shape gate dielectric layer on the U-shape trench, a U-shape gate region on the U-shape gate dielectric layer, a conducting matter in the U-shape gate region, and a cover dielectric layer on the conducting matter. The semiconductor structure may have a minimized size and when recess channels are formed thereby, the integration is accordingly improved without suffering from the short channel effect.

Abstract: Method for fabricating a self-aligned gate of a transistor including: forming a plurality of deep trench capacitors in a substrate, concurrently forming a surface strap and a contact pad on a surface of the substrate, wherein a spacing between the surface strap and the contact pad exposes a portion of an active area, filling the spacing with a dielectric layer, forming a photoresist pattern on the substrate, wherein the photoresist has an opening situated directly above the spacing between the surface strap and the contact pad, etching away the dielectric layer and a portion of a shallow trench isolation region through the opening thereby forming an upwardly protruding fin-typed channel structure, forming a gate dielectric layer on the upwardly protruding fin-typed channel structure, and forming a gate on the gate dielectric layer.

Abstract: A flash memory cell includes a substrate, a T-shaped control gate disposed above the substrate, a floating gate embedded in a lower recess of the T-shaped control gate, a dielectric layer between the T-shaped control gate and the floating gate; a cap layer above the T-shaped control gate, a control gate oxide between the T-shaped control gate and the substrate, a floating gate oxide between the floating gate and the substrate, a liner covering the cap layer and the floating gate, and a source/drain region adjacent to the floating gate. The floating gate has a vertical wall surface that is coplanar with one side of the dielectric layer.

Abstract: A method for forming a surface strap includes forming a deep trench capacitor having a conductive connection layer on its surface in the substrate and the conductive connection layer in contact with the conductive layer; forming a poly-Si layer covering the pad layer and the conductive connection layer; performing a selective ion implantation with an angle to make part of the poly-Si layer an undoped poly-Si layer; removing the undoped poly-Si layer to expose part of the conductive connection layer; etching the exposed conductive connection layer to form a recess; removing the poly-Si layer to make the exposed conductive connection layer a conductive connection strap; filling the recess with an insulation material to form a shallow trench isolation; exposing the conductive layer; and selectively removing the conductive layer to form a first conductive strap which forms the surface strap together with the conductive connection strap.

Abstract: A semiconductor component includes a substrate, two isolation structures, a conductor pattern and a dielectric layer. The isolation structures are disposed in the substrate, and each of the isolation structures has protruding portions protruding from the surface of the substrate. A trench is formed between the protruding portions. The included angle formed by the sidewall of the protruding portion and the surface of the substrate is an obtuse angle. The conductor pattern is disposed in the trench and fills the trench up. The dielectric layer is disposed between the conductor pattern and the substrate.

Abstract: A DRAM structure includes a substrate, a MOS transistor, a deep trench capacitor, a surface strap positioned on the surface of the substrate and interconnecting a drain of the MOS transistor and an electrode of the deep trench capacitor, wherein the sidewall and the top surface of the surface strap are covered with an insulating layer. A passing gate is positioned on the insulating layer.

Abstract: A method of fabricating self-aligned recess utilizing asymmetric poly spacer is disclosed. A semiconductor substrate having thereon a first pad layer and second pad layer is provided. A plurality of trenches is embedded in a memory array region of the semiconductor substrate. Each of the trenches includes a trench top layer that extrudes from a main surface of the semiconductor substrate. Asymmetric poly spacer is formed on one side of the extruding trench top layer and is used, after oxidized, as a mask for forming a recess in close proximity to the trenches.

Abstract: A checkerboard deep trench dynamic random access memory cell array layout is disclosed, which includes a substrate, a plurality of gate conductor lines disposed on the substrate, a plurality of checkerboard-arranged and staggered deep trench capacitor structures embedded in the substrate under the gate conductor lines, and a plurality of active areas formed in the substrate under the gate conductor lines, alternatively arranged with the deep trench capacitor structures, and electrically connected with an adjacent deep trench capacitor structure. The width of the parts of the gate conductor lines above the deep trench capacitor structures is narrower than that of the parts of the gate conductor lines above the active areas.

Abstract: A method for fabricating a vertical transistor. At least one deep trench is formed in a silicon substrate. A conductive structure and a trench top insulator are successively formed in the deep trench, in which the conductive structure comprises a first doping region and the trench top insulator is below the surface of the silicon substrate. An epitaxial silicon layer is formed on the surface of the silicon substrate. Ion implantation is performed in the epitaxial silicon layer to form a second doping region therein. A gate structure is formed on the trench top insulator, protruding from the surface of the epitaxial silicon layer and adjacent to the sidewalls of the epitaxial silicon layer and the deep trench. A capping layer is formed on the epitaxial silicon layer. The invention also discloses a memory device with a vertical transistor and a method for fabricating the same.

Abstract: A method for forming a semiconductor memory device with a recessed gate is disclosed. A substrate with a pad layer thereon is provided. The pad layer and the substrate are patterned to form at least two trenches. A deep trench capacitor is formed in each trench. A protrusion is formed on each deep trench capacitor, wherein a top surface level of each protrusion is higher than that of the pad layer. Spacers are formed on sidewalls of the protrusions, and the pad layer and the substrate are etched using the spacers and the protrusions as a mask to form a recess. A recessed gate is formed in the recess.

Abstract: A method for forming a recess. The method includes providing a substrate with two protrusions having a first side wall and a second side wall opposite to the first side wall disposed above the substrate, conformally forming a mask layer on the substrate and the protrusions, tilt implanting the mask layer using a first implanting mask adjacent to the first side wall of the protrusions, removing implanted portions of the mask layer to form a patterned mask layer, and etching the substrate using the patterned mask layer, thereby forming a recess.

Abstract: A method of fabricating a semiconductor device having a trench gate is provided. First, a semiconductor substrate having a trench etch mask thereon is provided. The semiconductor substrate is etched to form a trench having a sidewall and a bottom using the trench etch mask as a shield. Impurities are doped into the semiconductor substrate through the trench to form a doped region. The semiconductor substrate underlying the trench is etched to form an extended portion. A gate insulating layer is formed on the trench and the extended portion. A trench gate is formed in the trench and the extended portion.

Abstract: A method of fabricating self-aligned recess utilizing asymmetric poly spacer is disclosed. A semiconductor substrate having thereon a first pad layer and second pad layer is provided. A plurality of trenches is embedded in a memory array region of the semiconductor substrate. Each of the trenches includes a trench top layer that extrudes from a main surface of the semiconductor substrate. Asymmetric poly spacer is formed on one side of the extruding trench top layer and is used, after oxidized, as a mask for forming a recess in close proximity to the trenches.

Abstract: A method of forming a vertical memory device with a rectangular trench. First, a substrate covered by a photoresist layer is provided. Next, the photoresist layer is defined by a mask to form a rectangular opening, wherein the mask has two rectangular transparent patterns arranged with a predetermined interval. Next, the substrate is etched using the defined photoresist layer as a mask to form a single rectangular trench and the photoresist layer is then removed. Finally, a trench capacitor and a vertical transistor are successively formed in the rectangular trench to finish the vertical memory device.