Patents by Inventor Chung Yung
Chung Yung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170367563Abstract: An airbag tube apparatus has a hollow tube with a closed end and an open end. A side hole is disposed near the closed end; when matter leaves the airbag tube apparatus, it enters the hollow tube from the side hole and flows out of the open end. A balloon is attached to the hollow tube, and connected to a vent. The balloon in a large volume can flexibly fix animal tissue. A vent is connected to the balloon, a valve, and a pneumatic module to form an air inflator to inflate, hold and deflate the balloon. The valve opens and closes the liquid flow in the vent, and is controlled by a circuit module; the pneumatic module, providing inflating function, is controlled by the circuit module; the circuit module, has a microprocessor unit, a memory unit and an input-and-output unit.Type: ApplicationFiled: June 22, 2017Publication date: December 28, 2017Inventors: Chung-Yung HO, Chung-Chen HO, Hong-Fa HO
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Publication number: 20170023827Abstract: A reflective element is adapted for use in a backlight module, which includes a plurality of optical lens elements each being provided with a light emitting element. The reflective element includes a plurality of interconnecting reflective portions, each defining a through hole that is adapted for accommodating a corresponding one of the optical lens elements and a corresponding one of the light emitting elements, and being adapted for reflecting light incident from the corresponding one of the light emitting elements. A backlight module and a display device including the reflective element are also disclosed.Type: ApplicationFiled: October 7, 2016Publication date: January 26, 2017Inventors: Chung-Yung TAI, Wei-Hsuan CHEN, Fong-Ming LIU
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Patent number: 8956961Abstract: A semiconductor device includes: a substrate having a base and an array of semiconductor pillars extending from the base, the substrate being formed with a plurality of trenches, each of which extends into the base and has two opposing trench side walls; a first insulative liner layer formed on each of the trench side walls of each of the trenches and divided into upper and lower segments by a gap that leaves a bit-forming surface of each of the trench side walls uncovered by the first insulative liner layer; and a plurality of buried bit lines, each of which extends into the base from the bit-forming surface of a respective one of the trench side walls of each of the trenches.Type: GrantFiled: March 9, 2012Date of Patent: February 17, 2015Assignee: Rexchip Electronics CorporationInventors: Kazuaki Takesako, Wen-Kuei Hsu, Yoshinori Tanaka, Yukihiro Nagai, Chih-Wei Hsiung, Hirotake Fujita, Tomohiro Kadoya, Wei-Chih Liu, Hsuan-Yu Fang, Yu-Ling Huang, Meng-Hsien Chen, Chun-Chiao Tseng, Chung-Yung Ai, Yu-Shan Hsu, Wei-Che Chang, Chun-Hua Huang
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Patent number: 8788185Abstract: A method and system for estimating traffic information by using integration of location update events and call events uses a sample capturing and analyzing device to associate location area update (LAU) and call sample data of a plurality of mobile users. The sample data at least includes at least one LAU event of at least one mobile user of the plurality of mobile users, and call arrival (CA) or call completion (CC) events of at least one call. Based on the sample data, a computation device is used to determine the location information and time information of the at least one LAU event and the CA or CC event of the at least one call, and estimate traffic information of one or more designated roads according to the location information and time information.Type: GrantFiled: July 27, 2012Date of Patent: July 22, 2014Assignees: Industrial Technology Research Institute, Chunghwa Telecom Co., Ltd.Inventors: Sheng-Ying Yen, Chih-Yen Huang, Ya-Yun Cheng, Chien-Hsiang Chen, Chung-Yung Chia
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Publication number: 20140087372Abstract: Disclosed herein is a hairpin probe for detecting a target pathogenic microorganism in a sample. The hairpin probe includes a microbead and an oligonucleotide having its 3?-end coupled to the microbead. The oligonucleotide includes, from 5? to 3?, a Tag sequence hybridizable to a specific identification sequence of the pathogenic microorganism, an internal control sequence having at least four words each having 4 nucleotides with a 75% AT-content, an anti-Tag sequence being a reverse complement of the Tag sequence, and a tail having at least two consecutive thymidine residues. The Tag and anti-Tag sequences are operable to form a stem of the hairpin probe with the internal control sequence being a loop. Also disclosed herein are, a kit including the hairpin probe and a method for using the kit in the detection of a target pathogenic microorganism.Type: ApplicationFiled: September 27, 2012Publication date: March 27, 2014Applicant: CHUNG YUAN CHRISTIAN UNIVERSITYInventors: Chung-Yung CHEN, Tzong-Yuan WU
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Publication number: 20140011484Abstract: A method and system for estimating traffic information by using integration of location update events and call events uses a sample capturing and analyzing device to associate location area update (LAU) and call sample data of a plurality of mobile users. The sample data at least includes at least one LAU event of at least one mobile user of the plurality of mobile users, and call arrival (CA) or call completion (CC) events of at least one call. Based on the sample data, a computation device is used to determine the location information and time information of the at least one LAU event and the CA or CC event of the at least one call, and estimate traffic information of one or more designated roads according to the location information and time information.Type: ApplicationFiled: July 27, 2012Publication date: January 9, 2014Inventors: Sheng-Ying YEN, Chih-Yen Huang, Ya-Yun Cheng, Chien-Hsiang Chen, Chung-Yung Chia
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Patent number: 8557646Abstract: A method for fabricating a vertical transistor comprises steps: forming a plurality of first trenches in a substrate; sequentially epitaxially growing a first polarity layer and a channel layer inside the first trenches, and forming a first retard layer on the channel layer; etching the first retard layer and the channel layer along the direction vertical to the first trenches to form a plurality of pillars; respectively forming a gate on a first sidewall and a second sidewall of each pillar; removing the first retard layer on the pillar; and epitaxially growing a second polarity layer on the pillar. The present invention is characterized by using an epitaxial method to form the first polarity layer, the channel layer and the second polarity layer and has the advantage of uniform ion concentration distribution. Therefore, the present invention can fabricate a high-quality vertical transistor.Type: GrantFiled: March 1, 2012Date of Patent: October 15, 2013Assignee: Rexchip Electronics CorporationInventors: Meng-Hsien Chen, Chung-Yung Ai, Chih-Wei Hsiung
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Publication number: 20130234230Abstract: A semiconductor device includes: a substrate having a base and an array of semiconductor pillars extending from the base, the substrate being formed with a plurality of trenches, each of which extends into the base and has two opposing trench side walls; a first insulative liner layer formed on each of the trench side walls of each of the trenches and divided into upper and lower segments by a gap that leaves a bit-forming surface of each of the trench side walls uncovered by the first insulative liner layer; and a plurality of buried bit lines, each of which extends into the base from the bit-forming surface of a respective one of the trench side walls of each of the trenches.Type: ApplicationFiled: March 9, 2012Publication date: September 12, 2013Inventors: Kazuaki Takesako, Wen-Kuei Hsu, Yoshinori Tanaka, Yukihiro Nagai, Chih-Wei Hsiung, Hirotake Fujita, Tomohiro Kadoya, Wei-Chih Liu, Hsuan-Yu Fang, Yu-Ling Huang, Meng-Hsien Chen, Chun-Chiao Tseng, Chung-Yung Ai, Yu-Shan Hsu, Wei-Che Chang, Chun-Hua Huang
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Publication number: 20130230955Abstract: A method for fabricating a vertical transistor comprises steps: forming a plurality of first trenches in a substrate; sequentially epitaxially growing a first polarity layer and a channel layer inside the first trenches, and forming a first retard layer on the channel layer; etching the first retard layer and the channel layer along the direction vertical to the first trenches to form a plurality of pillars; respectively forming a gate on a first sidewall and a second sidewall of each pillar; removing the first retard layer on the pillar; and epitaxially growing a second polarity layer on the pillar. The present invention is characterized by using an epitaxial method to form the first polarity layer, the channel layer and the second polarity layer and has the advantage of uniform ion concentration distribution. Therefore, the present invention can fabricate a high-quality vertical transistor.Type: ApplicationFiled: March 1, 2012Publication date: September 5, 2013Inventors: Meng-Hsien CHEN, Chung-Yung Ai, Chih-Wei Hsiung
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Publication number: 20130193511Abstract: A vertical transistor structure comprises a substrate, a plurality of pillars formed on the substrate and spaced from each other, a plurality of trenches each formed between two adjacent pillars, a protection layer formed on the surface of a first side wall and the surface of a second side wall of the trench, a first gate and a second gate respectively formed on the protection layer of the first side wall and the second side wall, and a separation layer covering a bottom wall of the trench. The present invention uses the separation layer functioning as an etch stopping layer to the first gate and the second gate while being etched. Further, thickness of the separation layer is used to control the distance between the bottom wall and the first and second gates and define widths of the drain and the source formed in the pillar via ion implantation.Type: ApplicationFiled: January 26, 2012Publication date: August 1, 2013Inventors: Hsuan-Yu FANG, Wei-Chih Liu, Yu-Ling Huang, Meng-Hsien Chen, Chun-Chiao Tseng, Chung-Yung Ai, Yu-Shan Hsu, Wei-Che Chang, Chun-Hua Huang, Kazuaki Takesako, Tomohiro Kadoya, Wen Kuei Hsu, Hirotake Fujita, Yukihiro Nagai, Chih-Wei Hsiung, Yoshinori Tanaka
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Publication number: 20130157454Abstract: A self-aligned wet etching process comprises the steps of: etching a substrate having an etch protection layer on a surface thereof to form a plurality of trenches spaced from each other; and sequentially forming an insulating layer, an etch stop layer and a primary insulator in each trench, wherein the primary insulator is filled inside an accommodation space surrounded by the etch stop layer. During the wet etching process, the etch stop layer protects the primary insulator from being etched, whereby is achieved anisotropic wet etching. Further, the present invention expands the contact areas for electrically connecting with external circuits and exempts the electric contactors formed on the contact areas from short circuit caused by excessively etching the primary insulators.Type: ApplicationFiled: December 15, 2011Publication date: June 20, 2013Inventors: Wei-Che CHANG, Chun-Hua Huang, Chung-Yung Ai, Wei-Chih Liu, Hsuan-Yu Fang, Yu-Ling Huang, Meng-Hsien Chen, Chun-Chiao Tseng, Yu-Shan Hsu, Kazuaki Takesako, Hirotake Fujita, Tomohiro Kadoya, Wen Kuei Hsu, Chih-Wei Hsiung, Yukihiro Nagai, Yoshinori Tanaka
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Patent number: 8461056Abstract: A self-aligned wet etching process comprises the steps of: etching a substrate having an etch protection layer on a surface thereof to form a plurality of trenches spaced from each other; and sequentially forming an insulating layer, an etch stop layer and a primary insulator in each trench, wherein the primary insulator is filled inside an accommodation space surrounded by the etch stop layer. During the wet etching process, the etch stop layer protects the primary insulator from being etched, whereby is achieved anisotropic wet etching. Further, the present invention expands the contact areas for electrically connecting with external circuits and exempts the electric contactors formed on the contact areas from short circuit caused by excessively etching the primary insulators.Type: GrantFiled: December 15, 2011Date of Patent: June 11, 2013Assignee: Rexchip Electronics CorporationInventors: Wei-Che Chang, Chun-Hua Huang, Chung-Yung Ai, Wei-Chih Liu, Hsuan-Yu Fang, Yu-Ling Huang, Meng-Hsien Chen, Chun-Chiao Tseng, Yu-Shan Hsu, Kazuaki Takesako, Hirotake Fujita, Tomohiro Kadoya, Wen Kuei Hsu, Chih-Wei Hsiung, Yukihiro Nagai, Yoshinori Tanaka
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Patent number: 8407837Abstract: A foldable structure for a hospital bed contains two mounts, a bed frame, and a bed plane, each mount including two rotary positioning pieces, wherein each rotary positioning piece has a hole and an arcuate groove to axially connect the each rotary positioning piece with two coupling elements of the bed frame, such that the bed frame rotates relative to the two mounts, the each rotary positioning piece has two orifices corresponding to two ends of the arcuate groove so that a spring pin of each side of the bed frame is inserted into one of the two orifices of the each rotary positioning pieces, hence the spring pin is pushed out of the one of the two orifices of the each rotary positioning pieces, a coupling element in the arcuate groove rotates smoothly relative to a coupling element in the hole, thus retracting or expanding the bed frame easily.Type: GrantFiled: October 2, 2012Date of Patent: April 2, 2013Assignee: Nan Yi Shyh Co., Ltd.Inventors: Yu-Chieh Huang, Chung-Yung Huang, Chung-Yi Huang
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Patent number: 8358391Abstract: We disclose a new method of preparing liquid crystal alignment layers that can produce controllable pretilt angles from near 0 to near 90°. It is based on the stacking of two alignment materials sequentially, with the first one being continuous and the second one being discontinuous leaving part of the first layer exposed.Type: GrantFiled: May 6, 2009Date of Patent: January 22, 2013Assignee: The Hong Kong University of Science and TechnologyInventors: Hoi Sing Kwok, Yuet Wing Li, Chung Yung Lee
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Publication number: 20120008896Abstract: The present invention relates to an integrate optics for multiplexer transceiver module, comprising: a substrate, a multiplexer, a first waveguide coupling device, a second waveguide coupling device and a third waveguide coupling device. In the present invention, the semiconductor materials and the semiconductor process are used to integrate variety of optical devices on a single semiconductor substrate (chip) by way of modular design and miniaturization, so as to carry out an integrated optics communication framework with high efficiency and low cost. Moreover, in the present invention, a plurality of optical receivers are integrated on the substrate by means of flip-chip bonding, so that, not only the objective of integrating the optical devices is accomplished but also the intensity of laser optical signal is increased.Type: ApplicationFiled: June 10, 2011Publication date: January 12, 2012Applicant: NATIONAL TSING-HUA UNIVERSITYInventors: Ming-Chang Lee, Kai-Ning Ku, Chung-Yung Wang, Kuo-Chung Huang, Tsung-Chi Hsu, Chung-Hsin Fu, Lin-Yu Tai
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Publication number: 20110230236Abstract: The present invention discloses an integrated system for remote monitoring home appliances by a cell phone. In the integrated system, a cell phone sends an instruction message to a computer by a wireless network. A digital control disk connected with the computer generates a control signal in accordance with the instruction message. The control signal is sent by a wireless transceiver circuit to a home appliance. Moreover, a state signal that includes information of the home appliance operation can be sent to the digital control disk. Through the computer connecting to the wireless network, the cell phone is informed of the information of the home appliance operation. Thereby, the user can control the home appliances and acquire the current operation states of the home appliances by his/her cell phone.Type: ApplicationFiled: March 18, 2011Publication date: September 22, 2011Inventors: Chung-Yung Tsai, Wei-Hsiang Wang, Chih-Chiang Kuo
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Publication number: 20100185734Abstract: This present invention relates to a method for processing response messages, comprising a transmitter, first communication gateway, second communication gateway and a receiver, wherein the transmitter is connected with the first communication gateway, while the receiver is linked with the second communication gateway. When a message is transmitted by the transmitter via a mobile communication network to a remote receiver, the second communication gateway will transmit a response message to the transmitter after the transmitter receives the message. The first communication gateway will determine that the receiver does not receive the message successfully if it does not receive the response message within a given time period, and then transmit the message again or inform the administrator. In this way, it can help reduce the loss of property and life to enterprises and their employees caused by loss of messages.Type: ApplicationFiled: January 19, 2009Publication date: July 22, 2010Applicant: MOXA INC.Inventor: Chung-Yung Shen
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Patent number: 7724752Abstract: This specification discloses a communication system across networks and the method thereof for processing remote controls of devices in a private network from a public network. By providing a server end that contains correspondence relations between client ends and mobile ends in a public network, packets in the public network are automatically transmitted to devices in a private network according to the correspondence table in the server end for remote controls. The invention increases the convenience in managing devices in a private network.Type: GrantFiled: December 29, 2008Date of Patent: May 25, 2010Assignee: Moxa Inc.Inventors: Chung Yung Shen, Jer Hong Suen
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Publication number: 20090290613Abstract: An external cavity laser assembly includes an external chirped exit reflector configured to reduce changes in reflectivity, thereby improving linearity. The chirped exit reflector may be configured to provide a reflectivity profile with a substantially flat peak portion, for example, as compared to the reflectivity profile of a uniform period fiber Bragg grating. The chirped exit reflector may also be configured such that an optical cavity length of the external cavity laser is shorter for higher wavelengths, thereby reducing wavelength fluctuations and changes in reflectivity caused by wavelength fluctuations.Type: ApplicationFiled: May 21, 2008Publication date: November 26, 2009Applicant: APPLIED OPTOELECTRONICS, INC.Inventors: Jun Zheng, Chung-Yung Wang, Hung-Lun Chang
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Publication number: 20090279306Abstract: A lighting apparatus is disclosed. The lighting apparatus comprises a casing, at least one light source and a microstructure cover. The light source is disposed on one side of the casing. The microstructure cover is mounted on the casing opposite to the reflective face thereof. The microstructure cover has a plurality of guiding micro-structures to guide light and a plurality of dispersing micro-structures to disperse light.Type: ApplicationFiled: July 8, 2008Publication date: November 12, 2009Applicant: RADIANT OPTO-ELECTRONICS CORPORATIONInventors: Ying-Fu Wang, Yen-Chuan Chu, Yi-Jen Chiu, Chung-Yung Tai, Thung-Chi Wu