Patents by Inventor Chung-a Han

Chung-a Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240163299
    Abstract: A service providing device according to an embodiment of the present invention comprises: a collection unit for collecting mail information transmitted between one or more user terminals; a security threat inspection unit for performing matching of a mail security process corresponding to the mail information in stages according to a preset security threat architecture, inspecting the mail information according to the matched mail security process, and storing and managing mail security inspection information according to the inspection results; and an email security diagnosis service unit for calculating quantitative analysis information, corresponding to a threat level element classification reference of a mail system to be diagnosed, from the architecture processing information from the security threat inspection unit, and creating an email security diagnosis analysis report based on the quantitative analysis information to provide the email security diagnosis analysis reporting to a user terminal of a man
    Type: Application
    Filed: January 27, 2022
    Publication date: May 16, 2024
    Inventor: Chung Han KIM
  • Publication number: 20240164109
    Abstract: In an embodiment, a device includes: a word line extending in a first direction; a data storage layer on a sidewall of the word line; a channel layer on a sidewall of the data storage layer; a back gate isolator on a sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.
    Type: Application
    Filed: January 8, 2024
    Publication date: May 16, 2024
    Inventors: Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Feng-Cheng Yang, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20240162242
    Abstract: A display device according to one or more embodiments of the disclosure includes a pixel on a base layer; a gate driver configured to supply a gate control signal to the pixel through a gate line; pads including a first pad on the base layer and electrically connected to the pixel through a data line and a second pad on the base layer and electrically connected to the gate driver; and a protection circuit electrically connected to the pads. The protection circuit includes a first protection circuit electrically connected between the first pad and the pixel and a second protection circuit electrically connected between the second pad and the gate driver. The first protection circuit and the second protection circuit have different structures.
    Type: Application
    Filed: August 24, 2023
    Publication date: May 16, 2024
    Inventors: Young Ok PARK, Chung Han SHIM
  • Patent number: 11985830
    Abstract: A semiconductor device and method of manufacture are provided. In embodiments a memory array is formed by manufacturing portions of a word line during different and separate processes, thereby allowing the portions formed first to act as a structural support during later processes that would otherwise cause undesired damage to the structures.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Cheng Yang, Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Chung-Te Lin
  • Patent number: 11981851
    Abstract: A quantum dot including a core comprising a first semiconductor nanocrystal including a zinc chalcogenide and a semiconductor nanocrystal shell disposed on the surface of the core and comprising zinc, selenium, and sulfur. The quantum dot does not comprise cadmium, emits blue light, and may exhibit a digital diffraction pattern obtained by a Fast Fourier Transform of a transmission electron microscopic image including a (100) facet of a zinc blende structure. In an X-ray diffraction spectrum of the quantum dot, a ratio of a defect peak area with respect to a peak area of a zinc blende crystal structure is less than about 0.8:1. A method of producing the quantum dot, and an electroluminescent device including the quantum dot are also disclosed.
    Type: Grant
    Filed: November 11, 2022
    Date of Patent: May 14, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Woo Kim, Jin A Kim, Tae Hyung Kim, Kun Su Park, Yuho Won, Jeong Hee Lee, Eun Joo Jang, Hyo Sook Jang, Yong Seok Han, Heejae Chung
  • Publication number: 20240152880
    Abstract: A multi-channel payment method for a multi-channel payment system comprises the payer or the payee who initiated the payment request logs in to the multi-channel payment system; the payer or the payee who initiated the payment request placing an order in the multi-channel payment system, wherein the order comprises a designated payment gateway; the multi-channel payment system determining a predicted fee of the order according to the designated payment gateway, past order records, and a real-time exchange rate; the multi-channel payment system performing an anti-money laundering verification of the order; the payer reviewing the order and the predicted fee through a multiple auditing method; and the multi-channel payment system executing payment from the payer to the payee according to the order and the designated payment gateway, and storing a payment detail of the order.
    Type: Application
    Filed: February 13, 2023
    Publication date: May 9, 2024
    Applicant: OBOOK INC.
    Inventors: Chun-Kai Wang, Chung-Han Hsieh, Chun-Jen Chen, Po-Hua Lin, Wei-Te Lin, Pei-Hsuan Weng, Mei-Su Wang, I-Cheng Lin, Cheng-Wei Chen
  • Publication number: 20240154066
    Abstract: Embodiments provide an emissive display device including a light emitting diode that includes a first circuit part disposed in a display area and a cathode electrically connected to the first circuit part; and a non-emissive element that includes a second circuit part disposed in the display area and a cathode electrically connected to the second circuit part, and the cathode of the non-emissive element is separated from the cathode of the light emitting diode by a separator.
    Type: Application
    Filed: October 24, 2023
    Publication date: May 9, 2024
    Applicant: Samsung Display Co., LTD.
    Inventors: Chung Sock CHOI, Byung Han YOO, Yoo Min KO, Ju Chan PARK, Dae-Young LEE
  • Publication number: 20240139337
    Abstract: The present disclosure relates to a method for treating a cancer and/or cancer metastasis in a subject comprising administering to the subject irinotecan loaded in a mesoporous silica nanoparticle. The present disclosure also provides a conjugate comprising an agent loaded in a mesoporous silica nanoparticle (MSN) defining at least one pore and having at least one functional group on a sidewall of the at least one pore.
    Type: Application
    Filed: November 2, 2022
    Publication date: May 2, 2024
    Inventors: Cheng-Hsun WU, SI-HAN WU, YI-PING CHEN, RONG-LIN ZHANG, CHUNG-YUAN MOU, Yu-Tse LEE
  • Publication number: 20240142794
    Abstract: A stereo projection screen including a scattering screen having a scattering structure layer, a phase retardation layer disposed between the scattering structure layer and the polarized projector, and a metal reflection layer covering at least a part of the scattering structure layer is provided. The scattering structure layer and the phase retardation layer are arranged in a first display area and a second display area of the stereo projection screen. The metal reflection layer is arranged in at least one of the first display area and the second display area. A first image light beam having a first polarization state has a second polarization state after being transmitted to the first display area and leaving the stereo projection screen. A second image light beam having the first polarization state still has the first polarization state after being transmitted to the second display area and leaving the stereo projection screen.
    Type: Application
    Filed: October 23, 2023
    Publication date: May 2, 2024
    Applicant: Coretronic Corporation
    Inventors: Chung-Yang Fang, Wen-Chun Wang, Bo-Han Cheng
  • Patent number: 11971565
    Abstract: An absorption type near-infrared filter comprising a first multilayer film, a second multilayer film, and an absorption film, wherein in the ultraviolet band, the difference of between the wavelength with the transmittance at 80% of the absorbing film and the wavelength with the reflectivity at 80% of the first multilayer film falls in the range between 25 nm and 37 nm, the difference of between the wavelength with the transmittance at 50% of the absorbing film and the wavelength with the reflectivity at 50% of the first multilayer film falls in the range between 6 nm and 14 nm, and the difference of between the wavelength with the transmittance at 20% of the absorbing film and the wavelength with the reflectivity at 20% of the first multilayer film falls in the range between ?6 nm and 2.5 nm.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: April 30, 2024
    Assignees: PTOT (SUZHOU) INC., PLATINUM OPTICS TECHNOLOGY INC.
    Inventors: Chung-Han Lu, Hsiao-Ching Shen, Chun-Cheng Hsieh, Ming-Zhan Wang
  • Publication number: 20240138152
    Abstract: In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 25, 2024
    Inventors: Feng-Cheng Yang, Meng-Han Lin, Sheng-Chen Wang, Han-Jong Chia, Chung-Te Lin
  • Patent number: 11965522
    Abstract: An impeller includes a hub and a plurality of blades. The blades are arranged around the hub, and each blade includes a leading edge, a blade tip, a root portion, a trailing edge, a windward side and a leeward side. The windward side including a first turning point and a second turning point, a first vertical height difference is formed from the blade tip to the first turning point, and a second vertical height difference is formed from the first turning point to the second turning point, and the first vertical height difference is greater than the second vertical height difference. The impeller apparently reduces the noise.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: April 23, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Pei-Han Chiu, Chien-Ming Lee, Chung-Yuan Tsang, Chao-Fu Yang
  • Publication number: 20240128324
    Abstract: A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.
    Type: Application
    Filed: November 21, 2022
    Publication date: April 18, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Chih Lai, Shih-Min Chou, Nien-Ting Ho, Wei-Ming Hsiao, Li-Han Chen, Szu-Yao Yu, Chung-Yi Chiu
  • Publication number: 20240120563
    Abstract: A sensing block includes a block body having a plurality of slots through which electrode leads of battery cells pass, a plurality of sensing terminals installed between the plurality of slots on a front surface of the block body, a circuit board installed on the front surface of the block body, and a connector installed on the circuit board.
    Type: Application
    Filed: July 25, 2023
    Publication date: April 11, 2024
    Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATION, VALEO KAPEC CO., LTD.
    Inventors: Hyunchang Kang, Bum Jin Kim, Kyubin Chung, Seoha Kang, Ji Woong Han, Wan Choi, Houk Park, Jae Eun Kim
  • Publication number: 20240120018
    Abstract: A memory device, a failure bits detector, and a failure bits detection method thereof are provided. The failure bits detector includes a current generator, a current mirror, and a comparator. The current generator generates a first current according to a reference code. The current mirror mirrors the first current to generate a second current at a second end of the current mirror. The comparator compares a first voltage at a first input end with a second voltage at a second input end to generate a detection result.
    Type: Application
    Filed: October 5, 2022
    Publication date: April 11, 2024
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Chung-Han Wu, Che-Wei Liang, Chih-He Chiang, Shang-Chi Yang
  • Publication number: 20240105775
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first source/drain structure and a second source/drain structure over and in a substrate. The method includes forming a first gate stack, a second gate stack, a third gate stack, and a fourth gate stack over the substrate. Each of the first gate stack or the second gate stack is wider than each of the third gate stack or the fourth gate stack. The method includes forming a first contact structure and a second contact structure over the first source/drain structure and the second source/drain structure respectively. A first average width of the first contact structure is substantially equal to a second average width of the second contact structure.
    Type: Application
    Filed: February 9, 2023
    Publication date: March 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Yu CHIANG, Hsiao-Han LIU, Yuan-Hung TSENG, Chih-Yung LIN
  • Publication number: 20240105849
    Abstract: A method for forming a semiconductor structure is provided. The method for forming the semiconductor structure includes forming a fin structure over a substrate in a first direction, forming a first gate stack, a second gate stack and a third gate stack across the fin structure, removing the first gate stack to form a trench, depositing a cutting structure in the trench, and forming a first contact plug between the cutting structure and the second gate stack and a second contact plug between the second gate stack and the third gate stack. The fin structure is cut into two segments by the trench. A first dimension of the first contact plug in the first direction is greater than a second dimension of the second contact plug in the first direction.
    Type: Application
    Filed: February 10, 2023
    Publication date: March 28, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Da-Zhi ZHANG, Chun-An LU, Chung-Yu CHIANG, Po-Nien CHEN, Hsiao-Han LIU, Jhon-Jhy LIAW, Chih-Yung LIN
  • Publication number: 20240105521
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate having a base, a first fin, and a second fin over the base. The method includes forming a first trench in the base and between the first fin and the second fin. The method includes forming an isolation layer over the base and in the first trench. The first fin and the second fin are partially in the isolation layer. The method includes forming a first gate stack over the first fin and the isolation layer. The method includes forming a second gate stack over the second fin and the isolation layer. The method includes removing a bottom portion of the base. The isolation layer passes through the base after the bottom portion of the base is removed.
    Type: Application
    Filed: February 9, 2023
    Publication date: March 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Da-Zhi ZHANG, Chung-Pin HUANG, Po-Nien CHEN, Hsiao-Han LIU, Jhon-Jhy LIAW, Chih-Yung LIN
  • Patent number: D1011584
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: January 16, 2024
    Inventor: Chung Han Yu
  • Patent number: D1012344
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: January 23, 2024
    Inventor: Chung Han Yu