Abstract: An electronic device unlocking method is applied to a first electronic device and includes receiving operation information sent by a second electronic device; sending first information to the second electronic device when determining, based on the operation information, to unlock a to-be-unlocked object of the first electronic device, where the first information is used by the second electronic device to collect authentication information required for unlocking the to-be-unlocked object; obtaining authentication information from the second electronic device to perform authentication of a user; and unlocking the to-be-unlocked object of the first electronic device when the authentication of the user succeeds.

Abstract: A clock signal generator includes ramp and threshold voltage generators. The clock signal generator further includes a comparator configured to initiate a first phase of a clock signal based on the ramp and threshold voltages applied to its first and second inputs, respectively. The comparator is further configured to initiate a second phase of the clock signal based on the ramp and threshold voltages applied to its second and first inputs, respectively. Because the application of the ramp and threshold voltages to the inputs of the comparator is swapped per phase of the clock signal, any offset voltage in the comparator does not affect the period of the clock signal because they cancel out after two-half periods. This ensures that the clock signal has a substantially constant frequency. Other features include enabling the high power consuming comparator during a small window to achieve low jitter and low average power consumption.

Abstract: A boost and LDO hybrid converter with dual-loop control is disclosed. In some implementations, a hybrid converter includes an inductor having a first terminal to receive an input voltage and a second terminal; an n-type metal oxide semiconductor device (nMOS) having a drain coupled to the second terminal of the inductor; a p-type metal oxide semiconductor device (pMOS) having a gate, a drain, and a source, the source coupled to the second terminal of the inductor; an output capacitor having a first terminal coupled to the drain of the first pMOS; and a controller having a switch driver and a buffer, wherein the controller is configured to use the switch driver to drive the gate of the first pMOS in a boost mode and to use the buffer to drive the gate of the first pMOS in a low drop out (LDO) mode.

Abstract: A boost and LDO hybrid converter with dual-loop control is disclosed. In some implementations, a hybrid converter includes an inductor having a first terminal to receive an input voltage and a second terminal; an n-type metal oxide semiconductor device (nMOS) having a drain coupled to the second terminal of the inductor; a p-type metal oxide semiconductor device (pMOS) having a gate, a drain, and a source, the source coupled to the second terminal of the inductor; an output capacitor having a first terminal coupled to the drain of the first pMOS; and a controller having a switch driver and a buffer, wherein the controller is configured to use the switch driver to drive the gate of the first pMOS in a boost mode and to use the buffer to drive the gate of the first pMOS in a low drop out (LDO) mode.

Abstract: Certain aspects of the present disclosure relate to methods and apparatus for Multiple Input Single Inductor Multiple Output (MISIMO) power conversion for power management circuits. Certain aspects provide a method for controlling a power conversion circuit. The method includes selectively opening and closing one of a first switch, second, and third switch to cause a terminal coupled to an output of the third switch to carry a signal at a first voltage based on one or more parameters associated with a first voltage source and one or more parameters associated with a second voltage source. The method further includes selectively opening and closing one of the first switch and the second switch and a fourth switch to cause a terminal coupled to an output of the fourth switch to carry a signal at a second voltage based on each of the one or more parameters.

Abstract: A clock signal generator includes ramp and threshold voltage generators. The clock signal generator further includes a comparator configured to initiate a first phase of a clock signal based on the ramp and threshold voltages applied to its first and second inputs, respectively. The comparator is further configured to initiate a second phase of the clock signal based on the ramp and threshold voltages applied to its second and first inputs, respectively. Because the application of the ramp and threshold voltages to the inputs of the comparator is swapped per phase of the clock signal, any offset voltage in the comparator does not affect the period of the clock signal because they cancel out after two-half periods. This ensures that the clock signal has a substantially constant frequency. Other features include enabling the high power consuming comparator during a small window to achieve low jitter and low average power consumption.

Abstract: The present disclosure describes a power receiving unit for charging while in pre-overvoltage protection. In some aspects, reduced operation of an electronic implant device is initiated before resorting to overvoltage protection. In aspects, the electronic implant device has a power receiving unit capable of receiving power wirelessly from a wireless power transmitter. The power receiving unit can also detect an induced voltage and trigger pre-overvoltage protection when the detected voltage reaches a pre-overvoltage protection threshold. Additionally, a power management integrated circuit (PMIC) of the electronic implant device draws power from the power receiving unit to carry out corresponding functionality. The PMIC also obtains an indication when the detected voltage reaches the pre-overvoltage protection threshold. Based on the indication, the PMIC may reduce the power it draws from the power receiving unit to a predefined, reduced level instead of a normal operating level.

Abstract: In certain aspects, a method for providing electrical stimulation includes transferring energy from a battery to an electrode to charge the electrode, and, after the electrode is charged, transferring energy from the electrode to the battery to discharge the battery. The energy transferred from the electrode to the battery may include a portion of the energy transferred from the battery to the electrode.

Abstract: Disclosed is switching power supply that includes a pulse frequency modulation (PFM) mode of operation current feedback control. A reference current source is configured to output a reference current at one of several selectable levels. The level of the reference current may vary during operation of the current feedback control loop.

Abstract: In certain aspects, a method for providing electrical stimulation includes transferring energy from a battery to an electrode to charge the electrode, and, after the electrode is charged, transferring energy from the electrode to the battery to discharge the battery. The energy transferred from the electrode to the battery may include a portion of the energy transferred from the battery to the electrode.

Abstract: A switchable supply network for powering multiple digital islands. In one embodiment, a first digital island includes a first power collapsible circuit and a first retention circuit, and a second digital island includes a second power collapsible circuit and a second retention circuit. In a normal mode of operation, the first digital island is provided a first supply voltage and a second digital island is provided a second supply voltage higher than the first supply voltage. In a transition mode the second power collapsible circuit is powered down and the second supply voltage is lowered and provided to the second retention circuit. When the second supply voltage falls below the first supply voltage, the first power collapsible circuit is powered down. The second supply voltage is now provided only to the retention circuits, and is furthered lowered in a retention mode to a final retention voltage.

Abstract: The present disclosure includes circuits that have a switching regulator and methods of operating the circuits. The switching regulator may receive a switching signal that has a switching frequency. The circuit also includes a monitor circuit to monitor the switching frequency, and includes a reconfigurable inductance coupled to an output of the switching regulator. The monitor circuit may change the reconfigurable inductance. The circuit includes an amplifier to receive an envelope tracking signal. An output of the amplifier is coupled to the output of the switching regulator to provide a power supply voltage. The circuit may further include a switching generator circuit to produce the switching signal for the switching regulator based on an output current of the amplifier. The monitor circuit may compare a frequency of the envelope tracking signal to the switching frequency of the switching signal and accordingly change the reconfigurable inductance.

Abstract: In one embodiment, a circuit comprises a charge pump. A gain control circuit is configured to detect an input voltage and generate a gain control signal to change a gain of the charge pump to maintain the output voltage of the charge pump in a voltage range. A voltage to frequency converter is configured to detect the input voltage and change a frequency of a frequency control signal applied to the charge pump based in the detected input voltage to maintain the frequency in a frequency range so that the output voltage of the charge pump is maintained in the voltage range.

Abstract: A switchable supply network for powering multiple digital islands. In one embodiment, a first digital island includes a first power collapsible circuit and a first retention circuit, and a second digital island includes a second power collapsible circuit and a second retention circuit. In a normal mode of operation, the first digital island is provided a first supply voltage and a second digital island is provided a second supply voltage higher than the first supply voltage. In a transition mode the second power collapsible circuit is powered down and the second supply voltage is lowered and provided to the second retention circuit. When the second supply voltage falls below the first supply voltage, the first power collapsible circuit is powered down. The second supply voltage is now provided only to the retention circuits, and is furthered lowered in a retention mode to a final retention voltage.

Abstract: In one embodiment, a circuit comprises a first load circuit coupled to a first input voltage. A current sinking circuit is coupled to an output of the first load circuit. A second load circuit is coupled to ground. A current sourcing circuit is coupled between a second input voltage and an output of the second load circuit. A charge-recycling circuit is coupled between the output of the first load circuit and the output of the second load circuit to provide current from the current sinking circuit to the output of the current sourcing circuit to reduce current through the current sourcing circuit. The charge-recycling circuit can be a charge pump.

Abstract: Embodiments described herein relate to an improved circuit technique in a rail-to-rail input stage circuit utilizing non-complementary differential pairs with bias control designed to maintain a constant transconductance “gm” throughout an input common mode voltage range. The rail-to-rail input stage circuit comprises a first differential pair circuit, a level-shifted differential pair circuit coupled with the first differential pair circuit, and a constant transconductance generation circuit coupled with the level-shifted differential pair circuit. The constant transconductance generation circuit is configured to control the bias current conducting in the level-shifted differential pair circuit based on current conducting in the first differential pair circuit to maintain a constant transconductance in the rail-to-rail input stage circuit.

Abstract: The present disclosure includes switching regulator circuits and methods having reconfigurable inductance. In one embodiment, a circuit comprises a switching regulator, the switching regulator receiving a switching signal having a switching frequency, a monitor circuit to monitor the switching frequency, and a reconfigurable inductance at an output of the switching regulator, wherein the monitor circuit changes the reconfigurable inductance between a plurality of inductance values based on the switching frequency. In envelope tracking applications, an envelope tracking signal frequency and switching frequency are monitored to adjust a switching stage inductance.

Abstract: Disclosed is switching power supply that includes a pulse frequency modulation (PFM) mode of operation current feedback control. A reference current source is configured to output a reference current at one of several selectable levels. The level of the reference current may vary during operation of the current feedback control loop.

Abstract: Exemplary embodiments are related to switching power converters. A switching power converter may comprise a plurality of control unit configured for average current mode control, wherein each control unit of the plurality comprises a dedicated proportional control unit. The switching power converter may further comprise an integrator coupled to each control unit of the plurality of control unit and configured to convey a signal to each control unit.

Abstract: The present disclosure provides semiconductor packages and methods for fabricating semiconductor packages. The semiconductor package may comprise a semiconductor device mounted to a first substrate, a voltage regulator mounted to the first substrate and coupled to the semiconductor device, and an inductive element located on a perimeter of the semiconductor device and coupled to the voltage regulator, wherein the inductive element is formed by a plurality of interconnected conductive elements extending vertically from the first substrate.