Patents by Inventor Chun-Min Cheng
Chun-Min Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240139199Abstract: The present disclosure provides a use of a pharmaceutical composition including adenine and/or a pharmaceutically acceptable salt thereof in a manufacture of a medicament for treating diabetic ulcers, and the medicament can effectively accelerate and enhance wound healing of diabetic ulcers and prevent scar formation.Type: ApplicationFiled: March 25, 2022Publication date: May 2, 2024Inventors: Jen-Yi Chio, Han-Min Chen, Jiun-Tsai Lin, Yi-Fang Cheng, Guang-Huar Young, Chun-Fang Huang
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Publication number: 20230269938Abstract: A semiconductor structure includes a substrate, a common source plane disposed on the substrate, a plurality of memory cells vertically disposed on the substrate and electrically connected to the common source plane, a common source line disposed on the substrate and electrically connected to the common source plane, and an isolation pillar. The common source line extends along a first direction and has a first segment and a second segment. The isolation pillar interposes the first segment and the second segment of the common source line.Type: ApplicationFiled: February 23, 2022Publication date: August 24, 2023Inventors: Jung-Yi GUO, Chun-Min CHENG
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Patent number: 11362101Abstract: A three-dimensional memory device includes a plurality of conductive layers and insulating layers alternately formed to define a multi-layer stacked structure on a first region of a semiconductor substrate. The multi-layer stacked structure includes a stair structure and a non-stair structure. A plurality of memory structures are located in the non-stair structure to form a memory array region, and each memory structure passes through the conductive layers and the insulating layers. A plurality of bow-height adjustment features are located in a second region of the semiconductor substrate.Type: GrantFiled: March 5, 2020Date of Patent: June 14, 2022Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chien-Lan Chiu, Chun-Min Cheng
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Publication number: 20210280596Abstract: A three-dimensional memory device includes a plurality of conductive layers and insulating layers alternately formed to define a multi-layer stacked structure on a first region of a semiconductor substrate. The multi-layer stacked structure includes a stair structure and a non-stair structure. A plurality of memory structures are located in the non-stair structure to form a memory array region, and each memory structure passes through the conductive layers and the insulating layers. A plurality of bow-height adjustment features are located in a second region of the semiconductor substrate.Type: ApplicationFiled: March 5, 2020Publication date: September 9, 2021Inventors: Chien-Lan CHIU, Chun-Min CHENG
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Patent number: 10714491Abstract: A memory device and manufacturing method thereof are provided. The memory device includes a pair of stacked structures, a charge storage layer, and a channel layer. The stacked structures are disposed on a substrate. Each stacked structure includes gate layers and insulating layers stacked alternately, and a cap layer on the gate layers and the insulating layers. The charge storage layer is disposed on sidewalls of the stacked structures facing each other. The channel layer covers the charge storage layer, and has a top portion, a body portion, and a bottom portion. The top portion covers sidewalls of the cap layers of the stacked structures. The bottom portion covers a portion of the substrate located between the stacked structures. The body portion is connected between the top and bottom portions. Dopant concentrations of the top and bottom portions are respectively greater than a dopant concentration of the body portion.Type: GrantFiled: August 16, 2018Date of Patent: July 14, 2020Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chien-Lan Chiu, Chun-Min Cheng
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Publication number: 20200105782Abstract: A vertical channel structure including a substrate, a stack structure, and a channel structure is provided. The stack structure is disposed on the substrate. The channel structure is disposed in an opening that at least partially penetrates through the stack structure. The channel structure includes a first channel layer and a second channel layer. The first channel layer is disposed on a bottom of the opening. The second channel layer is disposed on the first channel layer. A resistance value of the first channel layer is less than a resistance value of the second channel layer.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Applicant: MACRONIX International Co., Ltd.Inventors: Jung-Yi Guo, Chun-Min Cheng
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Publication number: 20200058666Abstract: A memory device and manufacturing method thereof are provided. The memory device includes a pair of stacked structures, a charge storage layer, and a channel layer. The stacked structures are disposed on a substrate. Each stacked structure includes gate layers and insulating layers stacked alternately, and a cap layer on the gate layers and the insulating layers. The charge storage layer is disposed on sidewalls of the stacked structures facing each other. The channel layer covers the charge storage layer, and has a top portion, a body portion, and a bottom portion. The top portion covers sidewalls of the cap layers of the stacked structures. The bottom portion covers a portion of the substrate located between the stacked structures. The body portion is connected between the top and bottom portions. Dopant concentrations of the top and bottom portions are respectively greater than a dopant concentration of the body portion.Type: ApplicationFiled: August 16, 2018Publication date: February 20, 2020Applicant: MACRONIX International Co., Ltd.Inventors: Chien-Lan Chiu, Chun-Min Cheng
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Patent number: 10388664Abstract: An integrated circuit includes a multilayer stack, and a plurality of layered conductors extending in the multilayer stack and into a conductor layer beneath the multilayer stack. The layered conductor has a bottom conductor layer in ohmic electrical contact with the conductive layer in a substrate, an intermediate conductive liner layer over the bottom conductor layer and lining a portion of sidewall of the corresponding trench, and a top conductor layer on the top conductive liner layer.Type: GrantFiled: March 6, 2018Date of Patent: August 20, 2019Assignee: Macronix International Co., Ltd.Inventors: Yukai Huang, Chun Ling Chiang, Yung-Tai Hung, Chun Min Cheng, Tuung Luoh, Ling Wuu Yang, Ta-Hung Yang, Kuang-Chao Chen
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Patent number: 10340283Abstract: A process for fabricating a 3D memory is shown. Linear stacks, each of which includes alternately stacked gate lines and insulating layers, are formed. A charge trapping layer is formed covering the linear stacks. An amorphous semiconductor layer is formed on the charge trapping layer. An ultra-thin cap layer is formed on the amorphous semiconductor layer. The amorphous semiconductor layer is annealed to form a crystalline channel layer, wherein agglomeration of the material of the amorphous semiconductor layer is suppressed by then ultra-thin cap layer.Type: GrantFiled: January 5, 2018Date of Patent: July 2, 2019Assignee: MACRONIX International Co., Ltd.Inventors: Jung-Yi Guo, Chun-Min Cheng
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Patent number: 10312253Abstract: A method of forming a three-dimensional memory device is provided. Insulating layers and sacrificial layers are stacked alternatively on a substrate. At least one first opening is formed through the insulating layers and the sacrificial layers. Protection layers are formed on surfaces of the sacrificial layers exposed by the sidewall of the first opening. A charge storage layer is formed on the sidewall of the first opening and covers the protection layers. A channel layer is formed on the charge storage layer. The sacrificial layers and the protection layers are replaced with electrode layers. A three-dimensional memory device is further provided.Type: GrantFiled: March 14, 2017Date of Patent: June 4, 2019Assignee: MACRONIX International Co., Ltd.Inventors: Chun-Ling Chiang, Chun-Min Cheng, Jung-Yi Guo
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Patent number: 10217761Abstract: A semiconductor structure for three-dimensional memory device and a manufacturing method thereof are provided. The semiconductor structure is disposed on the substrate and has a plurality of openings penetrating through the semiconductor structure and extending into the substrate. The semiconductor structure includes a substrate, a stacked structure and an epitaxial layer. The stacked structure includes insulating layers and gate layers stacked alternatively. Each of the plurality of openings includes a first portion located above the surface of the substrate and a second portion located below the surface of the substrate. The aspect ratio of the second portion is more than 1. The epitaxial layer is disposed in each of the plurality of openings. The top surface of the epitaxial layer is between the top surface and the bottom surface of the i-th insulating layer as counted upward from the substrate, wherein i?2.Type: GrantFiled: November 22, 2017Date of Patent: February 26, 2019Assignee: MACRONIX International Co., Ltd.Inventors: Chun-Ling Chiang, Chun-Min Cheng, Ming-Tsung Wu
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Publication number: 20180269225Abstract: An integrated circuit includes a multilayer stack, and a plurality of layered conductors extending in the multilayer stack and into a conductor layer beneath the multilayer stack. The layered conductor has a bottom conductor layer in ohmic electrical contact with the conductive layer in a substrate, an intermediate conductive liner layer over the bottom conductor layer and lining a portion of sidewall of the corresponding trench, and a top conductor layer on the top conductive liner layer.Type: ApplicationFiled: March 6, 2018Publication date: September 20, 2018Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yukai HUANG, Chun Ling CHIANG, Yung-Tai HUNG, Chun Min CHENG, Tuung LUOH, Ling Wuu YANG, Ta-Hung YANG, Kuang-Chao CHEN
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Publication number: 20180269215Abstract: A method of forming a three-dimensional memory device is provided. Insulating layers and sacrificial layers are stacked alternatively on a substrate. At least one first opening is formed through the insulating layers and the sacrificial layers. Protection layers are formed on surfaces of the sacrificial layers exposed by the sidewall of the first opening. A charge storage layer is formed on the sidewall of the first opening and covers the protection layers. A channel layer is formed on the charge storage layer. The sacrificial layers and the protection layers are replaced with electrode layers. A three-dimensional memory device is further provided.Type: ApplicationFiled: March 14, 2017Publication date: September 20, 2018Applicant: MACRONIX International Co., Ltd.Inventors: Chun-Ling Chiang, Chun-Min Cheng, Jung-Yi Guo
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Publication number: 20180130822Abstract: A process for fabricating a 3D memory is shown. Linear stacks, each of which includes alternately stacked gate lines and insulating layers, are formed. A charge trapping layer is formed covering the linear stacks. An amorphous semiconductor layer is formed on the charge trapping layer. An ultra-thin cap layer is formed on the amorphous semiconductor layer. The amorphous semiconductor layer is annealed to form a crystalline channel layer, wherein agglomeration of the material of the amorphous semiconductor layer is suppressed by then ultra-thin cap layer.Type: ApplicationFiled: January 5, 2018Publication date: May 10, 2018Applicant: MACRONIX International Co., Ltd.Inventors: Jung-Yi Guo, Chun-Min Cheng
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Patent number: 9911754Abstract: A process for fabricating a 3D memory is shown. Linear stacks, each of which includes alternately stacked gate lines and insulating layers, are formed. A charge trapping layer is formed covering the linear stacks. An amorphous semiconductor layer is formed on the charge trapping layer. An ultra-thin cap layer is formed on the amorphous semiconductor layer. The amorphous semiconductor layer is annealed to form a crystalline channel layer, wherein agglomeration of the material of the amorphous semiconductor layer is suppressed by then ultra-thin cap layer.Type: GrantFiled: October 7, 2016Date of Patent: March 6, 2018Assignee: MACRONIX International Co., Ltd.Inventors: Jung-Yi Guo, Chun-Min Cheng
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Publication number: 20170125259Abstract: Provided are improved semiconductor memory devices and methods for manufacturing such semiconductor memory devices. The methods may include two or more nitride removal steps during formation of gate layers in vertical memory cells. The two or more nitride removal steps may allow for wider gate layers increasing the gate fill-in, reducing the occurrence of voids, and thereby improving the word line resistance.Type: ApplicationFiled: November 4, 2015Publication date: May 4, 2017Inventors: Jr-Meng WANG, Chih-Yuan WU, Kuanf-Wen LIU, Jung-Yi GUO, Chun-Min CHENG
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Patent number: 9627220Abstract: Provided are improved semiconductor memory devices and methods for manufacturing such semiconductor memory devices. The methods may include two or more nitride removal steps during formation of gate layers in vertical memory cells. The two or more nitride removal steps may allow for wider gate layers increasing the gate fill-in, reducing the occurrence of voids, and thereby improving the word line resistance.Type: GrantFiled: November 4, 2015Date of Patent: April 18, 2017Assignee: Macronix International Co., Ltd.Inventors: Jr-Meng Wang, Chih-Yuan Wu, Kuanf-Wen Liu, Jung-Yi Guo, Chun-Min Cheng
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Patent number: 9461063Abstract: A method for forming a semiconductor structure is provided. The method includes following steps. First, a stack of alternate conductive layers and insulating layers is formed on a buffer layer on a buried layer. Next, a first opening is formed through the stack and through a portion of the buffer layer. Thereafter, a spacer is formed on a sidewall of the first opening.Type: GrantFiled: May 6, 2015Date of Patent: October 4, 2016Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Erh-Kun Lai, Chun-Min Cheng, Kuang-Hao Chiang
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Publication number: 20160190153Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate, a plurality of fin structures, a plurality of conductor liner layers, a charge storage layer, a plurality of first conductor layers, and a plurality of filling pillars. The fin structures are disposed on the substrate, and a trench is formed between two adjacent fin structures. Each of the conductor liner layers covers a portion of sidewalls and a portion of top surfaces of the fin structures. The charge storage layer is disposed between the fin structures and the conductor liner layers. The first conductor layers cover the conductor liner layers and are electrically connected to the conductor liner layers. The filling pillars are disposed in the trenches and between the conductor liner layers and the first conductor layers.Type: ApplicationFiled: December 24, 2014Publication date: June 30, 2016Inventors: Jung-Yi Guo, Chun-Min Cheng
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Patent number: 9337208Abstract: A method of manufacturing a semiconductor device is provided. Gate structures are formed on a substrate, and a first dielectric layer having grooves is formed between two adjacent gate structures. An upper surface of the first dielectric layer is lower than an upper surface of the gate structures. Afterwards, an intermediate layer is formed to cover the gate structures, the first dielectric layer, and the grooves, and openings are formed therein. Each opening is formed between two adjacent gate structures, and the first dielectric layer is removed through the opening. Next, a second dielectric layer is formed on the intermediate layer, so as to define an air gap between two adjacent gate structures. Furthermore, a semiconductor device is provided.Type: GrantFiled: September 24, 2014Date of Patent: May 10, 2016Assignee: MACRONIX International Co., Ltd.Inventors: Pei-Ci Jhang, Chun-Min Cheng