Abstract: A non-volatile memory device includes a floating gate with pyramidal-shaped silicon nanocrystals as electron storage elements. Electrons tunnel from the pyramidal-shaped silicon nanocrystals through a gate oxide layer to a control gate of the non-volatile memory device. The pyramidal shape of each silicon nanocrystal concentrates an electrical field at its peak to facilitate electron tunneling. This allows an erase process to occur at a lower tunneling voltage and shorter tunneling time than that of prior art devices.

Abstract: A method of manufacture of an integrated circuit system includes: providing a second layer between a first layer and a third layer; forming an active device over the third layer; forming the third layer to form an island region underneath the active device; forming the second layer to form a floating second layer with an undercut beneath the island region; and depositing a fourth layer around the island region and the floating second layer.

Abstract: A device includes a substrate with a device region on which a transistor is formed. The device region includes active edge regions and an active center region which have different oxidation growth rates. A growth rate modifier (GRM) comprising dopants which modifies oxidation growth rate is employed to produce a gate oxide layer which has a uniform thickness. The GRM may enhance or retard the oxidation growth, depending on the type of dopants used. Fluorine dopants enhance oxidation growth rate while nitrogen dopants retard oxidation growth rate.

Abstract: A method of forming a semiconductor device is presented. The method includes providing a substrate. The method further includes forming a gate stack having a gate electrode on the substrate, which includes forming a metal gate electrode layer. A buffer gate electrode layer is formed on top of the metal gate electrode layer and a top gate electrode layer having a poly-silicon alloy is formed over the metal gate electrode layer.

Abstract: A method of manufacturing an integrated circuit system includes: providing a substrate having a channel region; forming a gate stack over a portion of the channel region with the gate stack having a floating gate for storing an electrical charge; forming a source recess in the substrate adjacent to the gate stack; and forming a source by layering a first bandgap material in the source recess.

Abstract: A method (and semiconductor device) of fabricating a semiconductor device provides a field effect transistor (FET) with reduced gate contact resistance (and series resistance) for improved device performance. An impurity is implanted or deposited in the gate stack in an impurity region between the metal gate electrode and the gate contact layer. An anneal process is performed that converts the impurity region into a segregation layer which lowers the schottky barrier height (SBH) of the interface between the metal gate electrode (e.g., silicide) and gate contact layer (e.g., amorphous silicon). This results in lower gate contact resistance and effectively lowers the device's AC Reff.

Abstract: FinFET devices are formed with body contact structures enabling the fabrication of such devices having different gate threshold voltages (Vt). A body contact layer is formed to contact the gate electrode (contact) enabling a forward body bias and a reduction in Vt. Two example methods of fabrication (and resulting structures) are provided. In one method, the gate electrode (silicon-based) and body contact layer (silicon) are connected by growing epitaxy which merges the two structures forming electrical contact. In another method, a via is formed that intersects with the gate electrode (suitable conductive material) and body contact layer and is filled with conductive material to electrically connect the two structures. As a result, various FinFETs with different Vt can be fabricated for different applications.

Abstract: A method (and semiconductor device) of fabricating a semiconductor device adjusts gate threshold (Vt) of a field effect transistor (FET) with raised source/drain (S/D) regions. A halo region is formed in a two-step process that includes implanting dopants using conventional implantation techniques and implanting dopants at a specific twist angle. The dopant concentration in the halo region near the active edge of the raised S/D regions is higher and extends deeper than the dopant concentration within the interior region of the raised S/D regions. As a result, Vt near the active edge region is adjusted and different from the Vt at the active center regions, thereby achieving same or similar Vt for a FET with different width.

Abstract: A method for forming a device is presented. A substrate prepared with a feature having first and second adjacent surfaces is provided. A device layer is formed on the first and second adjacent surfaces of the feature. A first portion of the device layer over the first adjacent surface includes nano-crystals, whereas a second portion of the device layer over the second adjacent surface is devoid of nano-crystals.

Abstract: A method for forming a semiconductor device is disclosed. The method includes providing a substrate prepared with a second gate structure. An inter-gate dielectric is formed on the substrate and over the second gate. A first gate is also formed. The first gate is adjacent to and separated from the second gate by the inter-gate dielectric. The substrate is patterned to form a split gate structure with the first and second adjacent gates. The split gate structure is provided with an e-field equalizer adjacent to the first gate. The e-field equalizer improves uniformity of e-field across the first gate during operation.

Abstract: A non-volatile memory device includes a floating gate with pyramidal-shaped silicon nanocrystals as electron storage elements. Electrons tunnel from the pyramidal-shaped silicon nanocrystals through a gate oxide layer to a control gate of the non-volatile memory device. The pyramidal shape of each silicon nanocrystal concentrates an electrical field at its peak to facilitate electron tunneling. This allows an erase process to occur at a lower tunneling voltage and shorter tunneling time than that of prior art devices.

Abstract: A circuit having a circuit control terminal, a primary circuit and a protection circuit is provided. The primary circuit includes a primary control terminal and a primary gate oxide of a thickness T1. The primary control terminal is coupled to the circuit control terminal. The protection circuit having a protection control terminal is coupled to the primary circuit. The protection circuit includes a protection gate oxide of a second thickness T2 which is less than T1. The protection gate oxide reduces plasma induced damage in the primary circuit.

Abstract: A method of manufacture of an integrated circuit system includes: providing a mesa over a substrate; forming a trench in the substrate adjacent the mesa; forming a second gate and a charge storage material along a trench sidewall; and forming a first gate from the mesa.

Abstract: A method of manufacture of an integrated circuit system includes: providing a second layer between a first layer and a third layer; forming an active device over the third layer; forming the third layer to form an island region underneath the active device; forming the second layer to form a floating second layer with an undercut beneath the island region; and depositing a fourth layer around the island region and the floating second layer.

Abstract: A circuit having a circuit control terminal, a primary circuit and a protection circuit is provided. The primary circuit includes a primary control terminal and a primary gate oxide of a thickness T1. The primary control terminal is coupled to the circuit control terminal. The protection circuit having a protection control terminal is coupled to the primary circuit. The protection circuit includes a protection gate oxide of a second thickness T2 which is less than T1. The protection gate oxide reduces plasma induced damage in the primary circuit.