Patents by Inventor Chuong A. Tran

Chuong A. Tran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11745267
    Abstract: An additive manufacturing (AM) method is provided. The method includes performing a laser powder bed fusion (L-PBF) process on the powder layer. Then, a first surface roughness value of the powder layer after the L-PBF process is obtained to generate a first surface profile. An absorptivity and a set of re-melting process parameters data are used to perform a heat transfer simulation. A second surface profile of the powder layer after laser re-melting is obtained by using the first surface profile and a low-pass filter. Then, the set of re-melting process parameters data is adjusted iteratively to perform the heat transfer simulation until a second surface roughness value predicted from the second surface profile is smaller than or equal to a surface roughness threshold, thereby obtaining optimal values of re-melting process parameters for performing a re-melting process to reduce a surface roughness of a powder layer after the L-PBF process.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: September 5, 2023
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Hong-Chuong Tran, Yu-Lung Lo, Haw-Ching Yang, Fan-Tien Cheng
  • Publication number: 20220247147
    Abstract: A semiconductor laser and a fabrication method therefor. The method comprises: providing a heat sink motherboard, and cutting the heat sink motherboard to form a plurality of heat sink substrates (300) (S11); providing an epitaxial wafer (200) (S12); bonding the plurality of heat sink substrates (300) to the epitaxial wafer (200) in an array to form a plurality of gaps parallel to the direction of resonant cavities (210) and perpendicular to the direction of the resonant cavities (210) (S13); dividing the epitaxial wafer (200) along the gaps to obtain a plurality of laser chips (S14); and stacking the plurality of laser chips, and coating the plurality of stacked laser chips to form a plurality of semiconductor lasers (S15).
    Type: Application
    Filed: October 16, 2019
    Publication date: August 4, 2022
    Inventors: CHAO-CHEN CHENG, ANH CHUONG TRAN
  • Publication number: 20220136125
    Abstract: Disclosed are a manufacturing method for a laser chip and a laser chip. The manufacturing method comprises: step S1, forming a first electroplating substrate on an epitaxial layer; step S2, forming an organic pattern layer on the first electroplating substrate, wherein the pattern layer defines a hollowed-out area and a part of the first electroplating substrate is exposed to the pattern layer by means of the hollowed-out area; step S3, forming a first metal coating on the first electroplating substrate, wherein the first metal coating completely covers the pattern layer and the part of the first electroplating substrate not covered by the pattern layer; and step S4, removing the pattern layer to have a hollow channel formed between the first metal coating and the first electroplating substrate, wherein the channel is provided with at least one inlet and at least one outlet running through the first metal coating.
    Type: Application
    Filed: December 11, 2019
    Publication date: May 5, 2022
    Applicants: SHENZHEN LASER INSTITUTE, SHENZHEN LASER INSTITUTE
    Inventors: ANH CHUONG TRAN, CHAO-CHEN CHENG
  • Publication number: 20220059986
    Abstract: A semiconductor laser chip and a preparation method therefor, the method comprising: providing an epitaxial wafer (100), the epitaxial wafer (100) comprising a plurality of resonant cavities (110) arranged in parallel; providing a heat sink substrate (200); attaching the epitaxial wafer (100) to the heat sink substrate (200) so as to form a first chip semi-finished product (10); performing first division on the first chip semi-finished product (10) in the direction perpendicular to the resonant cavities (110) so as to divide the first chip semi-finished product (10) into a plurality of second chip semi-finished products (20); and performing second division on the second chip semi-finished products (20) in the direction parallel to the resonant cavities (110) so as to divide the second chip semi-finished products (20) into a plurality of semiconductor laser chips (30) such that the semiconductor laser chips (30) comprise at least one laser bar.
    Type: Application
    Filed: October 16, 2019
    Publication date: February 24, 2022
    Inventors: CHAO-CHEN CHENG, ANH CHUONG TRAN
  • Publication number: 20210402476
    Abstract: An additive manufacturing (AM) method is provided. The method includes performing a laser powder bed fusion (L-PBF) process on the powder layer. Then, a first surface roughness value of the powder layer after the L-PBF process is obtained to generate a first surface profile. An absorptivity and a set of re-melting process parameters data are used to perform a heat transfer simulation. A second surface profile of the powder layer after laser re-melting is obtained by using the first surface profile and a low-pass filter. Then, the set of re-melting process parameters data is adjusted iteratively to perform the heat transfer simulation until a second surface roughness value predicted from the second surface profile is smaller than or equal to a surface roughness threshold, thereby obtaining optimal values of re-melting process parameters for performing a re-melting process to reduce a surface roughness of a powder layer after the L-PBF process.
    Type: Application
    Filed: June 24, 2021
    Publication date: December 30, 2021
    Inventors: Hong-Chuong TRAN, Yu-Lung LO, Haw-Ching YANG, Fan-Tien CHENG
  • Patent number: 11110651
    Abstract: A method of performing powder bed fusion process is provided. A powder bed and a group of information of the powder bed are obtained. A powder bed simulation is performed to obtain a thickness of the powder bed and a packing density. Then, a group of parameters of a laser is obtained. A Ray Tracing simulation for the powder layer and a heat transfer simulation are performed. A first surrogate model is constructed to obtain first processing maps. The points in the first processing maps with the depths of the melt pool that are greater than a predetermined depth value and smaller than a laser beam radius are a first group of parameter values. A parameter setting operation is performed by using the first group of parameter values. A laser melting operation is performed, and a temperature distribution is measured by using an infrared thermal camera.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: September 7, 2021
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Yu-Lung Lo, Hong-Chuong Tran
  • Publication number: 20200198230
    Abstract: A method of performing powder bed fusion process is provided. A powder bed and a group of information of the powder bed are obtained. A powder bed simulation is performed to obtain a thickness of the powder bed and a packing density. Then, a group of parameters of a laser is obtained. A Ray Tracing simulation for the powder layer and a heat transfer simulation are performed. A first surrogate model is constructed to obtain first processing maps. The points in the first processing maps with the depths of the melt pool that are greater than a predetermined depth value and smaller than a laser beam radius are a first group of parameter values. A parameter setting operation is performed by using the first group of parameter values. A laser melting operation is performed, and a temperature distribution is measured by using an infrared thermal camera.
    Type: Application
    Filed: September 12, 2019
    Publication date: June 25, 2020
    Inventors: Yu-Lung LO, Hong-Chuong TRAN
  • Patent number: 8680534
    Abstract: A vertical light-emitting diode (VLED) includes a metal substrate, a p-electrode coupled to the metal substrate, a p-contact coupled to the p-electrode, a p-GaN portion coupled to the p-electrode, an active region coupled to the p-GaN portion, an n-GaN portion coupled to the active region, and a phosphor layer coupled to the n-GaN portion.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: March 25, 2014
    Assignee: Semileds Corporation
    Inventors: Chuong A Tran, Trung Tri Doan
  • Publication number: 20120032184
    Abstract: A vertical light-emitting diode (VLED) includes a metal substrate, a p-electrode coupled to the metal substrate, a p-contact coupled to the p-electrode, a p-GaN portion coupled to the p-electrode, an active region coupled to the p-GaN portion, an n-GaN portion coupled to the active region, and a phosphor layer coupled to the n-GaN portion.
    Type: Application
    Filed: September 7, 2011
    Publication date: February 9, 2012
    Inventors: CHUONG A. TRAN, TRUNG T. DOAN
  • Publication number: 20110284866
    Abstract: A light emitting diode (LED) device having a substantially conformal wavelength-converting layer for producing uniform white light and a method of making said LED at both the wafer and individual die levels are provided. The LED device includes a metal substrate, a p-type semiconductor coupled to the metal substrate, an active region coupled to the p-type semiconductor, an n-type semiconductor coupled to the active region, and a wavelength converting layer coupled to the n-type semiconductor.
    Type: Application
    Filed: July 26, 2011
    Publication date: November 24, 2011
    Inventors: CHUONG A. TRAN, Trung T. Doan, Jui-Kang Yen, Yung-Wei Chen
  • Patent number: 8012774
    Abstract: A light emitting diode (LED) device having a substantially conformal wavelength-converting layer for producing uniform white light and a method of making said LED at both the wafer and individual die levels are provided. The LED device includes a metal substrate, a p-type semiconductor coupled to the metal substrate, an active region coupled to the p-type semiconductor, an n-type semiconductor coupled to the active region, and a wavelength-converting layer coupled to the n-type semiconductor.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: September 6, 2011
    Assignee: SemiLEDs Optoelectronics Co., Ltd.
    Inventors: Chuong A. Tran, Trung T. Doan, Jui-Kang Yen, Yung-Wei Chen
  • Patent number: 7781247
    Abstract: A method of producing one or more vertical light-emitting diode (VLED) dies having a light-emitting diode (LED) stack comprising Group III-Group V combinations of elements (e.g., GaN, AlN, InN, AlGaN, InGaN, and InAlGaN) and a metal substrate is provided. The techniques include forming an InGaN or InAlGaN interface layer above a suitable growth-supporting substrate, such as sapphire or silicon carbide (SiC), and forming the LED stack above the interface layer. Such an interface layer may absorb a majority of the energy from a laser pulse used during laser lift-off of the growth-supporting substrate in an effort to prevent damage to the light emitting layers of the LED stack, which may result in improved brightness performance over VLED dies produced with conventional buffer layers.
    Type: Grant
    Filed: October 26, 2006
    Date of Patent: August 24, 2010
    Assignee: SemiLEDs Optoelectronics Co., Ltd.
    Inventor: Anh Chuong Tran
  • Patent number: 7615789
    Abstract: A vertical light-emitting diode (VLED) structure that may impart increased luminous efficiency over conventional LEDs and VLEDs is described. As additional benefits, some embodiments may have less susceptibility to electrostatic discharge (ESD) and higher manufacturing yields than conventional devices. To accomplish these benefits, embodiment of the invention may utilize a spacer or other means to separate the p-doped layer from the active layer, thereby increasing the distance between the active layer and the reflective layer within the VLED structure.
    Type: Grant
    Filed: May 9, 2006
    Date of Patent: November 10, 2009
    Assignee: SemiLEDs Optoelectronics Co., Ltd.
    Inventor: Anh Chuong Tran
  • Publication number: 20080099780
    Abstract: A method of producing one or more vertical light-emitting diode (VLED) dies having a light-emitting diode (LED) stack comprising Group III-Group V combinations of elements (e.g., GaN, AlN, InN, AlGaN, InGaN, and InAlGaN) and a metal substrate is provided. The techniques include forming an InGaN or InAlGaN interface layer above a suitable growth-supporting substrate, such as sapphire or silicon carbide (SiC), and forming the LED stack above the interface layer. Such an interface layer may absorb a majority of the energy from a laser pulse used during laser lift-off of the growth-supporting substrate in an effort to prevent damage to the light emitting layers of the LED stack, which may result in improved brightness performance over VLED dies produced with conventional buffer layers.
    Type: Application
    Filed: October 26, 2006
    Publication date: May 1, 2008
    Inventor: ANH CHUONG TRAN
  • Publication number: 20070228404
    Abstract: A vertical light emitting diode (LED) includes a metal substrate; a p-electrode coupled to the metal substrate; a p-contact coupled to the p-electrode; a p-GaN portion coupled to the p electrode; an active region coupled to the p-GaN portion; an n-GaN portion coupled to the active region; and a phosphor layer coupled to the n-GaN.
    Type: Application
    Filed: March 27, 2007
    Publication date: October 4, 2007
    Inventors: Chuong Tran, Trung Doan
  • Publication number: 20070166851
    Abstract: Systems and methods are disclosed for fabricating a semiconductor light-emitting diode (LED) device by forming an n-doped gallium nitride (n-GaN) layer on the LED device and roughening the surface of the n-GaN layer to extract light from an interior of the LED device.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 19, 2007
    Inventors: Chuong Tran, Trung Doan, Chen-Fu Chu, Hao-Chun Cheng, Feng-Hsu Fan
  • Publication number: 20070099319
    Abstract: Systems and methods are disclosed for fabricating a semiconductor light emitting diode (LED) device by forming an n-gallium nitride (n-GaN) layer on the LED device and roughening the surface of the n-GaN layer to extract light from an interior of the LED device.
    Type: Application
    Filed: December 21, 2006
    Publication date: May 3, 2007
    Inventors: Chuong Tran, Trung Doan
  • Publication number: 20070001178
    Abstract: A light emitting diode (LED) device having a substantially conformal wavelength-converting layer for producing uniform white light and a method of making said LED at both the wafer and individual die levels are provided. The LED device includes a metal substrate, a p-type semiconductor coupled to the metal substrate, an active region coupled to the p-type semiconductor, an n-type semiconductor coupled to the active region, and a wavelength converting layer coupled to the n-type semiconductor.
    Type: Application
    Filed: September 8, 2006
    Publication date: January 4, 2007
    Inventors: Chuong Tran, Trung Doan, Jui-Kang Yen, Yung-Wei Chen
  • Publication number: 20060237594
    Abstract: Vibrations due to excitation of the natural modes of an aircraft's body are suppressed by an active multi-axis modal suppression system. Dedicated sensors are positioned in the aircraft at optimal locations for sensing modal induced vibrations. The sensor produced signals are processed through control logic which, in response thereto, and in response to aircraft inertial, velocity and altitude related signals produces output control signals. The control signals effect control surface deployment creating forces to suppress the natural mode induced vibrations on multiple geometric axis's. More particularly, symmetric and anti-symmetric control surface deployments are used on one or more geometric axis's to damp lateral, longitudinal, vertical and most importantly torsional vibrational modes.
    Type: Application
    Filed: July 12, 2005
    Publication date: October 26, 2006
    Inventors: Kioumars Najmabadi, Chuong Tran, John Ho
  • Publication number: 20060157721
    Abstract: A vertical light emitting diode (LED) includes a metal substrate; a p-electrode coupled to the metal substrate; a p-contact coupled to the p-electrode; a p-GaN portion coupled to the p electrode; an active region coupled to the p-GaN portion; an n-GaN portion coupled to the active region; and a phosphor layer coupled to the n-GaN.
    Type: Application
    Filed: January 11, 2005
    Publication date: July 20, 2006
    Inventors: Chuong Tran, Trung Doan