Patents by Inventor Chushiro Kusano
Chushiro Kusano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9263559Abstract: A radio communication device includes a power amplifier having a semiconductor device formed with a plurality of unit transistors. Base electrodes of the unit transistors are connected with each other by a base line, and an input capacitor is connected to the base line such that the input capacitor is commonly and electrically connected to the base electrodes of a plurality of the unit transistors.Type: GrantFiled: August 27, 2014Date of Patent: February 16, 2016Assignee: Murata Manufacturing Co., Ltd.Inventors: Satoshi Sasaki, Yasunari Umemoto, Yasuo Osone, Tsutomu Kobori, Chushiro Kusano, Isao Ohbu, Kenji Sasaki
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Publication number: 20140361406Abstract: A radio communication device includes a power amplifier having a semiconductor device formed with a plurality of unit transistors. Base electrodes of the unit transistors are connected with each other by a base line, and an input capacitor is connected to the base line such that the input capacitor is commonly and electrically connected to the base electrodes of a plurality of the unit transistors.Type: ApplicationFiled: August 27, 2014Publication date: December 11, 2014Inventors: Satoshi SASAKI, Yasunari UMEMOTO, Yasuo OSONE, Tsutomu KOBORI, Chushiro KUSANO, Isao OHBU, Kenji SASAKI
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Patent number: 8860093Abstract: A technology which allows a reduction in the thermal resistance of a semiconductor device used in a radio communication device, and the miniaturization thereof is provided. For example, the semiconductor device can include a plurality of unit transistors Q, transistor formation regions 3a, 3b, and 3e each having a first number (e.g., seven) of the unit transistors Q, and transistor formation regions 3c and 3d each having a second number (e.g., four) of the unit transistors Q. The transistor formation regions 3c and 3d are located between the transistor formation regions 3a, 3b, 3e, and 3f, and the first number is larger than the second number.Type: GrantFiled: June 29, 2012Date of Patent: October 14, 2014Assignee: Murata Manufacturing Co., Ltd.Inventors: Satoshi Sasaki, Yasunari Umemoto, Yasuo Osone, Tsutomu Kobori, Chushiro Kusano, Isao Ohbu, Kenji Sasaki
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Patent number: 8742499Abstract: In a semiconductor chip in which LDMOSFET elements for power amplifier circuits used for a power amplifier module are formed, a source bump electrode is disposed on an LDMOSFET formation region in which a plurality of source regions, a plurality of drain regions and a plurality of gate electrodes for the LDMOSFET elements are formed. The source bump electrode is formed on a source pad mainly made of aluminum via a source conductor layer which is thicker than the source pad and mainly made of copper. No resin film is interposed between the source bump electrode and the source conductor layer.Type: GrantFiled: October 29, 2009Date of Patent: June 3, 2014Assignee: Murata Manufacturing Co., Ltd.Inventors: Shizuki Nakajima, Hiroyuki Nagai, Yuji Shirai, Hirokazu Nakajima, Chushiro Kusano, Yu Hasegawa, Chiko Yorita, Yasuo Osone
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Publication number: 20120261799Abstract: A technology which allows a reduction in the thermal resistance of a semiconductor device used in a radio communication device, and the miniaturization thereof is provided. For example, the semiconductor device can include a plurality of unit transistors Q, transistor formation regions 3a, 3b, and 3e each having a first number (e.g., seven) of the unit transistors Q, and transistor formation regions 3c and 3d each having a second number (e.g., four) of the unit transistors Q. The transistor formation regions 3c and 3d are located between the transistor formation regions 3a, 3b, 3e, and 3f, and the first number is larger than the second number.Type: ApplicationFiled: June 29, 2012Publication date: October 18, 2012Inventors: Satoshi SASAKI, Yasunari UMEMOTO, Yasuo OSONE, Tsutomu KOBORI, Chushiro KUSANO, Isao OHBU, Kenji SASAKI
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Patent number: 8227836Abstract: A technology which allows a reduction in the thermal resistance of a semiconductor device and the miniaturization thereof is provided. The semiconductor device has a plurality of unit transistors Q, transistor formation regions 3a, 3b, and 3e each having a first number (e.g., seven) of the unit transistors Q, and transistor formation regions 3c and 3d each having a second number (e.g., four) of the unit transistors Q. The transistor formation regions 3c and 3d are located between the transistor formation regions 3a, 3b, 3e, and 3f, and the first number is larger than the second number.Type: GrantFiled: October 15, 2009Date of Patent: July 24, 2012Assignee: Murata Manufacturing Co., Ltd.Inventors: Satoshi Sasaki, Yasunari Umemoto, Yasuo Osone, Tsutomu Kobori, Chushiro Kusano, Isao Ohbu, Kenji Sasaki
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Patent number: 8072001Abstract: A heterojunction bipolar transistor with InGaP as the emitter layer and capable of both reliable electrical conduction and thermal stability wherein a GaAs layer is inserted between the InGaP emitter layer and AlGaAs ballast resistance layer, to prevent holes reverse-injected from the base layer from diffusing and reaching the AlGaAs ballast resistance layer.Type: GrantFiled: September 10, 2010Date of Patent: December 6, 2011Assignee: Renesas Electronics CorporationInventors: Isao Ohbu, Chushiro Kusano, Yasunari Umemoto, Atsushi Kurokawa
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Publication number: 20100327980Abstract: A heterojunction bipolar transistor with InGaP as the emitter layer and capable of both reliable electrical conduction and thermal stability wherein a GaAs layer is inserted between the InGaP emitter layer and AlGaAs ballast resistance layer, to prevent holes reverse-injected from the base layer from diffusing and reaching the AlGaAs ballast resistance layer.Type: ApplicationFiled: September 10, 2010Publication date: December 30, 2010Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Isao OHBU, Chushiro KUSANO, Yasunari UMEMOTO, Atsushi KUROKAWA
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Patent number: 7804109Abstract: A heterojunction bipolar transistor with InGaP as the emitter layer and capable of both reliable electrical conduction and thermal stability wherein a GaAs layer is inserted between the InGaP emitter layer and AlGaAs ballast resistance layer, to prevent holes reverse-injected from the base layer from diffusing and reaching the AlGaAs ballast resistance layer.Type: GrantFiled: March 22, 2007Date of Patent: September 28, 2010Assignee: Renesas Electronics CorporationInventors: Isao Ohbu, Chushiro Kusano, Yasunari Umemoto, Atsushi Kurokawa
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Publication number: 20100109052Abstract: In a semiconductor chip in which LDMOSFET elements for power amplifier circuits used for a power amplifier module are formed, a source bump electrode is disposed on an LDMOSFET formation region in which a plurality of source regions, a plurality of drain regions and a plurality of gate electrodes for the LDMOSFET elements are formed. The source bump electrode is formed on a source pad mainly made of aluminum via a source conductor layer which is thicker than the source pad and mainly made of copper. No resin film is interposed between the source bump electrode and the source conductor layer.Type: ApplicationFiled: October 29, 2009Publication date: May 6, 2010Inventors: Shizuki NAKAJIMA, Hiroyuki NAGAI, Yuji SHIRAI, Hirokazu NAKEJIMA, Chushiro KUSANO, Yu HASEGAWA, Chiko YORITA, Yasuo OSONE
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Publication number: 20100032720Abstract: A technology which allows a reduction in the thermal resistance of a semiconductor device and the miniaturization thereof is provided. The semiconductor device has a plurality of unit transistors Q, transistor formation regions 3a, 3b, and 3e each having a first number (e.g., seven) of the unit transistors Q, and transistor formation regions 3c and 3d each having a second number (e.g., four) of the unit transistors Q. The transistor formation regions 3c and 3d are located between the transistor formation regions 3a, 3b, 3e, and 3f, and the first number is larger than the second number.Type: ApplicationFiled: October 15, 2009Publication date: February 11, 2010Inventors: Satoshi SASAKI, Yasunari Umemoto, Yasuo Osone, Tsutomu Kobori, Chushiro Kusano, Isao Ohbu, Kenji Sasaki
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Patent number: 7622756Abstract: A technology which allows a reduction in the thermal resistance of a semiconductor device and the miniaturization thereof is provided. The semiconductor device has a plurality of unit transistors Q, transistor formation regions 3a, 3b, and 3e each having a first number (seven) of the unit transistors Q, and transistor formation regions 3c and 3d each having a second number (four) of the unit transistors Q. The transistor formation regions 3c and 3d are located between the transistor formation regions 3a, 3b, 3e, and 3f and the first number is larger than the second number.Type: GrantFiled: December 28, 2005Date of Patent: November 24, 2009Assignee: Renesas Technology Corp.Inventors: Satoshi Sasaki, Yasunari Umemoto, Yasuo Osone, Tsutomu Kobori, Chushiro Kusano, Isao Ohbu, Kenji Sasaki
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Publication number: 20090194792Abstract: A semiconductor device has an external wiring for GND formed over an underside surface of a wiring substrate. A plurality of via holes connecting to the external wiring for GND are formed to penetrate the wiring substrate. A first semiconductor chip of high power consumption, including HBTs, is mounted over a principal surface of the wiring substrate. The emitter bump electrode of the first semiconductor chip is connected in common with emitter electrodes of a plurality of HBTs formed in the first semiconductor chip. The emitter bump electrode is extended in a direction in which the HBTs line up. The first semiconductor chip is mounted over the wiring substrate so that a plurality of the via holes are connected with the emitter bump electrode. A second semiconductor chip lower in heat dissipation value than the first semiconductor chip is mounted over the first semiconductor chip.Type: ApplicationFiled: March 27, 2009Publication date: August 6, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventors: Satoru Konishi, Tsuneo Endo, Hirokazu Nakajima, Yasunari Umemoto, Satoshi Sasaki, Chushiro Kusano, Yoshinori Imamura, Atsushi Kurokawa
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Patent number: 7511315Abstract: A semiconductor device has an external wiring for GND formed over an underside surface of a wiring substrate. A plurality of via holes connecting to the external wiring for GND are formed to penetrate the wiring substrate. A first semiconductor chip of high power consumption, including HBTs, is mounted over a principal surface of the wiring substrate. The emitter bump electrode of the first semiconductor chip is connected in common with emitter electrodes of a plurality of HBTs formed in the first semiconductor chip. The emitter bump electrode is extended in a direction in which the HBTs line up. The first semiconductor chip is mounted over the wiring substrate so that a plurality of the via holes are connected with the emitter bump electrode. A second semiconductor chip lower in heat dissipation value than the first semiconductor chip is mounted over the first semiconductor chip.Type: GrantFiled: April 19, 2005Date of Patent: March 31, 2009Assignee: Renesas Technology Corp.Inventors: Satoru Konishi, Tsuneo Endo, Hirokazu Nakajima, Yasunari Umemoto, Satoshi Sasaki, Chushiro Kusano, Yoshinori Imamura, Atsushi Kurokawa
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Patent number: 7256434Abstract: A heterojunction bipolar transistor with InGaP as the emitter layer and capable of both reliable electrical conduction and thermal stability wherein a GaAs layer is inserted between the InGaP emitter layer and AlGaAs ballast resistance layer, to prevent holes reverse-injected from the base layer from diffusing and reaching the AlGaAs ballast resistance layer.Type: GrantFiled: December 23, 2004Date of Patent: August 14, 2007Assignee: Renesas Technology Corp.Inventors: Isao Ohbu, Chushiro Kusano, Yasunari Umemoto, Atsushi Kurokawa
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Publication number: 20070164316Abstract: A heterojunction bipolar transistor with InGaP as the emitter layer and capable of both reliable electrical conduction and thermal stability wherein a GaAs layer is inserted between the InGaP emitter layer and AlGaAs ballast resistance layer, to prevent holes reverse-injected from the base layer from diffusing and reaching the AlGaAs ballast resistance layer.Type: ApplicationFiled: March 22, 2007Publication date: July 19, 2007Inventors: Isao Ohbu, Chushiro Kusano, Yasunari Umemoto, Atsushi Kurokawa
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Publication number: 20060157825Abstract: The invention is directed to improve resistance to destruction of a semiconductor device. A protection circuit having a plurality of bipolar transistors which are Darlington connected between outputs (collector and emitter) of an amplification circuit of a high output is electrically connected in parallel with the amplification circuit. The amplification circuit has a plurality of unit HBTs (Heterojunction Bipolar Transistors) which are connected in parallel with each other. The protection circuit has a two-stage configuration including a first group of a protection circuit having a plurality of bipolar transistors Q1 to Q5 and a second group of a protection circuit having a plurality of bipolar transistors.Type: ApplicationFiled: March 16, 2006Publication date: July 20, 2006Inventors: Yasunari Umemoto, Hideyuki Ono, Tomonori Tanoue, Yasuo Ohsone, Isao Ohbu, Chushiro Kusano, Atsushi Kurokawa, Masao Yamane
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Publication number: 20060138460Abstract: A technology which allows a reduction in the thermal resistance of a semiconductor device and the miniaturization thereof is provided. The semiconductor device has a plurality of unit transistors Q, transistor formation regions 3a, 3b, and 3e each having a first number (seven) of the unit transistors Q, and transistor formation regions 3c and 3d each having a second number (four) of the unit transistors Q. The transistor formation regions 3c and 3d are located between the transistor formation regions 3a, 3b, 3e, and 3f and the first number is larger than the second number.Type: ApplicationFiled: December 28, 2005Publication date: June 29, 2006Inventors: Satoshi Sasaki, Yasunari Umemoto, Yasuo Osone, Tsutomu Kobori, Chushiro Kusano, Isao Ohbu, Kenji Sasaki
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Publication number: 20060138459Abstract: Provided is a semiconductor device equipped with HBTs capable of satisfying both thermal stability and reliability and having improved electrostatic breakdown voltage. The HBT according to the present invention is obtained by successively forming, over the main surface of a substrate made of a compound semiconductor, a sub-collector layer, a collector layer, a base layer, an emitter layer, a collector electrode electrically connected to the collector layer, a base electrode electrically connected to the base layer, an emitter mesa layer formed over the emitter layer and electrically connected to the emitter layer, and an emitter electrode electrically connected to the emitter mesa layer. The emitter mesa layer has a semiconductor layer made of an n type GaAs layer, a high concentration semiconductor layer made of an n+ type GaAs layer over the semiconductor layer and a ballast resistor layer made of an n type InGaAs layer over the high concentration semiconductor layer.Type: ApplicationFiled: December 27, 2005Publication date: June 29, 2006Inventors: Atsushi Kurokawa, Isao Ohbu, Yasunari Umemoto, Satoshi Sasaki, Chushiro Kusano, Yoshinori Imamura
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Patent number: 7045877Abstract: The invention is directed to improve resistance to destruction of a semiconductor device. A protection circuit having a plurality of bipolar transistors which are Darlington connected between outputs (collector and emitter) of an amplification circuit of a high output is electrically connected in parallel with the amplification circuit. The amplification circuit has a plurality of unit HBTs (Heterojunction Bipolar Transistors) which are connected in parallel with each other. The protection circuit has a two-stage configuration including a first group of a protection circuit having a plurality of bipolar transistors Q1 to Q5 and a second group of a protection circuit having a plurality of bipolar transistors.Type: GrantFiled: April 23, 2003Date of Patent: May 16, 2006Assignee: Renesas Technology Corp.Inventors: Yasunari Umemoto, Hideyuki Ono, Tomonori Tanoue, Yasuo Ohsone, Isao Ohbu, Chushiro Kusano, Atsushi Kurokawa, Masao Yamane