Abstract: A method of detecting delamination in an integrated circuit package structure, the method includes forming a plurality of through vias over a carrier substrate; placing a device die over the carrier substrate and between the through vias, wherein the device die comprises a metal pillar; forming a molding material surrounding the device die and the through vias; forming a testing metal line extending along a top surface of the molding material and past an interface between the device die and the molding material; applying a current to the testing metal line; detecting an electrical signal of the testing metal line during the applying the current to the testing metal line; and determining, based on the detected electrical signal of the testing metal line, whether a delamination occurs between the device die and the molding material.

Abstract: An integrated circuit package structure includes a device die having a plurality of metal pillars, a molding material directly in contact with at least one side surface of the device die, a first dielectric layer disposed on the device die and on the molding material, and a testing pad disposed in the first dielectric layer and directly in contact with an interface between the device die and the molding material. The testing pad is electrical isolated from the metal pillars.

Abstract: An integrated circuit package structure includes a device die having a plurality of metal pillars, a molding material directly in contact with at least one side surface of the device die, a first dielectric layer disposed on the device die and on the molding material, and a testing pad disposed in the first dielectric layer and directly in contact with an interface between the device die and the molding material. The testing pad is electrical isolated from the metal pillars.

Abstract: An integrated defect yield management and query system for a semiconductor wafer fabrication process is disclosed. A local area network connects various testing devices for testing defect conditions of wafers, a defect yield management server and a client device. After inspection, these devices generate a plurality of process records corresponding to each of the semiconductor wafers. The defect yield management server retrieves the process records through the local area network. These process records are stored in a database divided into a plurality of fields, wherein each field corresponds to a specific defect property of the semiconductor wafers. Therefore, these acquired on-line data and their related history records can be accessed by using an inquiring interface, and the client device can effectively poll the process records stored in the database of the defect yield management server.

Abstract: The present invention discloses a method for forming a fin-type DRAM stacked capacitor that has improved charge capacity by first depositing multiple layers of different insulating materials on a preprocessed semiconductor substrate, then dry etching a contact opening through the multiple layers of insulating materials to form a node contact on the substrate, and then wet etching the contact opening in an etchant that has different etch rates for the different insulating materials exposed in the contact opening such that a zig-zag configuration in the contact opening is formed for producing a capacitor has increased surface area and therefore increased charge capacity. Suitable insulating layers utilized are doped oxide layers and non-doped oxide layers which can be etched at different etch rates when an etchant of SC1 is used.

Abstract: A method for forming an anti-reflective-coating(ARC) layer is described. This ARC layer performs not only in its capacity to reduce reflections from its subjacent metal layer during the metal patterning photoresist exposure, but also serves as an effective etch inhibitor during subsequent via etching. Of particular importance is the ability provided by this ARC layer to sustain its etch resistance during considerable over etching such as is required when vias of different depths are to be opened. The ARC layer differs from the conventional titanium nitride ARC layer in that it has a base layer of titanium below the titanium nitride portion. It is this titanium layer and an optional intermediate Ti rich layer that sustains the over etch. Additionally, the titanium forms an improved bonding with the metal beneath providing reduced via contact resistance and greater via stability and consistency.

Abstract: The inspection and measurement of critical dimensions of patterned features during the manufacture of sub-micron integrated circuits relies heavily upon the scanning-electron-microscope(SEM). This instrument is capable of quick, clean, and accurate measurements of features on large in-process silicon wafers. However, such features are frequently isolated from the electrical ground of the microscope by virtue of their circuit design. This creates a charge build up from the electron beam in the SEM and causes distorted and indistinct images, incapable of being measured. Also, such static charge build-up can be destructive to certain circuit elements. This invention teaches the use of independent inspection test structures, fabricated in wafer saw kerf regions or within designated test sites, especially designed to provide a reduction or elimination of charge build up during SEM observation.

Abstract: A method for preventing bubble formation over source/drain active areas in p-channel MOSFETs is described. Bubble formation occurs when the source/drain areas and silicon containing gate electrodes are implanted with BF.sub.2.sup.+ molecule ions following an anisotropic LDD spacer etch using a plasma. It is found that the plasma causes the silicon surface to become prone to adsorption of BF.sub.2.sup.+ molecule ions during the source/drain/gate implantation. These adsorbed species are released and form bubbles during reflow of a subsequently deposited glass layer. The invention performs the spacer etch only partially with the anisotropic plasma and completes the spacer formation with a wet etch. The active silicon and gate electrode surfaces are thus not damaged by the plasma. Consequently adsorption of BF.sub.2.sup.+ molecule ions is inhibited and bubble formation does not occur during reflow.

Abstract: A device and a method of manufacture of a semiconductor device on a semiconductor substrate including an SRAM cell with a resistor comprises forming a first polycrystalline silicon containing layer on the semiconductor substrate, patterning and etching the first polycrystalline silicon containing layer to form steps on either side thereof, forming a dielectric layer over the first polycrystalline silicon containing layer with the steps on either side of the first polycrystalline silicon containing layer, forming a blanket of a second polycrystalline silicon containing layer extending over the interpolysilicon layer, and ion implanting the second polycrystalline silicon containing layer in a blanket implant of a light dose of dopant including ion implanting resistive regions with far higher resistivity in the regions over the steps.

Abstract: The inspection and measurement of critical dimensions of patterned features during the manufacture of sub-micron integrated circuits relies heavily upon the scanning-electron-microscope(SEM). This instrument is capable of quick, clean, and accurate measurements of features on large in-process silicon wafers. However, such features are frequently isolated from the electrical ground of the microscope by virtue of their circuit design. This creates a charge build up from the electron beam in the SEM and causes distorted and indistinct images, incapable of being measured. Also, such static charge build-up can be destructive to certain circuit elements. This invention teaches the use of independent inspection test structures, fabricated in wafer saw kerf regions or within designated test sites, especially designed to provide a reduction or elimination of charge build up during SEM observation.

Abstract: A method is provided for improving the performance characteristics of the MOS devices contained within an integrated circuit that has been subjected to a rapid thermal anneal. After the rapid thermal anneal the integrated circuit is heated for more than about 30 minutes at a temperature of more than about 430.degree. C. in a gaseous atmosphere that contains hydrogen, typically forming gas.

Abstract: A device and a method of manufacture of a semiconductor device on a semiconductor substrate including an SRAM cell with a resistor comprises forming a first polycrystalline silicon containing layer on the semiconductor substrate, patterning and etching the first polycrystalline silicon containing layer to form steps on either side thereof, forming a dielectric layer over the first polycrystalline silicon containing layer with the steps on either side of the first polycrystalline silicon containing layer, forming a blanket of a second polycrystalline silicon containing layer extending over the interpolysilicon layer, and ion implanting the second polycrystalline silicon containing layer in a blanket implant of a light dose of dopant including ion implanting resistive regions with far higher resistivity in the regions over the steps.

Abstract: A new method of forming a tapered polysilicon etching profile in the manufacture of a thin film transistor integrated circuit is described. A layer of polysilicon is deposited over the surface of a semiconductor substrate. Ions are implanted into the polysilicon layer whereby the upper half of the polysilicon layer is damaged by the presence of the ions within the layer. The polysilicon layer is anisotropically etched. The polysilicon layer is isotropically etched whereby the damaged upper portion of the layer is etched faster than is the undamaged lower portion resulting in a tapered polysilicon layer. A layer of gate oxide is deposited over the surface of the tapered polysilicon layer. Then the thin film transistor body is formed. A layer of amorphous silicon is deposited over the surface of the gate oxide layer. The amorphous silicon layer is recrystallized to yield larger grain sizes.

Abstract: A method is described for forming multiple metal, spin-on-glass metallurgy with substantially free field inversion. A pattern of device regions are formed with a pattern of gate dielectric and gate electrode structures which are isolated from one another. A first passivation layer is formed over the patterns. The multilayer metallurgy is formed thereover by opening a pattern of openings through the passivation layer to some of the regions. A first metallurgy layer is deposited and patterned in contact with the pattern of openings. A first silicon oxide via dielectric layer is formed over the pattern of first metallurgy layer. A spin-on-glass layer is formed over the via dielectric layer and the layer is cured. A second oxide via dielectric layer is formed thereover. Openings are formed in the second via, spin-on-glass and first via layers. A second metallurgy layer is deposited and patterned in contact with the openings to make contact to the first metallurgy. A second dielectric layer is formed thereover.