Patents by Inventor Chytra Pawashe

Chytra Pawashe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11056356
    Abstract: Techniques and mechanisms for bonding a first wafer to a second wafer in the presence of a fluid, the viscosity of which is greater than a viscosity of air at standard ambient temperature and pressure. In an embodiment, a first surface of the first wafer is brought into close proximity to a second surface of the second wafer. The fluid is provided between the first surface and the second surface when a first region of the first surface is made to contact a second region of the second surface to form a bond. The viscosity of the fluid mitigates a rate of propagation of the bond along a wafer surface, which in turn mitigates wafer deformation and/or stress between wafers. In another embodiment, the viscosity of the fluid is changed dynamically while the bond propagates between the first surface and the second surface.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: July 6, 2021
    Assignee: Intel Corporation
    Inventors: Brennen K. Mueller, Daniel Pantuso, Mauro J. Kobrinsky, Chytra Pawashe, Myra McDonnell
  • Patent number: 10886153
    Abstract: Micro pick-and-bond heads, assembly methods, and device assemblies. In, embodiments, micro pick-and-bond heads transfer micro device elements, such as (micro) LEDs, en masse from a source substrate to a target substrate, such as a LED display substrate. Anchor and release structures on the source substrate enable device elements to be separated from a source substrate, while pressure sensitive adhesive (PSA) enables device elements to be temporarily affixed to pedestals of a micro pick-and bond head. Once the device elements are permanently affixed to a target substrate, the PSA interface may be defeated through peeling and/or thermal decomposition of an interface layer.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Peter L. Chang, Chytra Pawashe, Michael C. Mayberry, Jia-Hung Tseng
  • Publication number: 20200303191
    Abstract: Embodiments herein describe techniques for bonded wafers that includes a first wafer bonded with a second wafer, and a stress compensation layer in contact with the first wafer or the second wafer. The first wafer has a first stress level at a first location, and a second stress level different from the first stress level at a second location. The stress compensation layer includes a first material at a first location of the stress compensation layer that induces a third stress level at the first location of the first wafer, a second material different from the first material at a second location of the stress compensation layer that induces a fourth stress level different from the third stress level at the second location of the first wafer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 18, 2019
    Publication date: September 24, 2020
    Inventors: Anant JAHAGIRDAR, Chytra PAWASHE, Aaron LILAK, Myra MCDONNELL, Brennen MUELLER, Mauro KOBRINSKY
  • Patent number: 10720345
    Abstract: Techniques and mechanisms for forming a bond between two wafers. In an embodiment, a first wafer and a second wafer are positioned with respective wafer holders, and are deformed to form a first deformation of the first wafer and a second deformation of the second wafer. The first deformation and the second deformation are symmetrical with respect to a centerline which is between the first wafer and the second wafer. A portion of the first deformation is made to contact, and form a bond with, another portion of the second deformation. The bond is propagated along respective surfaces of the wafers to form a coupling therebetween. In another embodiment, one of the wafer holders comprises one of an array of elements to locally heat or cool a wafer, or an array of displacement stages to locally deform said wafer.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: July 21, 2020
    Assignee: Intel Corporation
    Inventors: Mauro J. Kobrinsky, Myra McDonnell, Brennen K. Mueller, Chytra Pawashe, Daniel Pantuso, Paul B. Fischer, Lance C. Hibbeler, Martin Weiss
  • Patent number: 10707186
    Abstract: Techniques and mechanisms for forming a bond between wafers using a compliant layer. In an embodiment, a layer or layers of one or more compliant materials is provided on a first surface of a first wafer, and the one or more compliant layers are subsequently bonded to a second surface of a second wafer. The bonded wafers are heated to an elevated temperature at which a compliant layer exhibits non-elastic deformations to facilitate relaxation of stresses caused by wafer distortions. In another embodiment, a material of the compliant layer exhibits viscoelastic behavior at room temperature, wherein stress is mitigated by allowing wafer distortion to relax at room temperature.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Mauro J. Kobrinsky, Jasmeet S. Chawla, Stefan Meister, Myra McDonnell, Chytra Pawashe, Daniel Pantuso
  • Publication number: 20200066595
    Abstract: Fin-based transistor structures, such as finFET and nanowire transistor structures, are disclosed. The fins have a morphology including a wave pattern and/or one or more ridges and/or nodules which effectively mitigate fin collapse, by limiting the inter-fin contact during a fin collapse condition. Thus, while the fins may temporarily collapse during wet processing, the morphology allows the collapsed fins to recover back to their uncollapsed state upon drying. The fin morphology may be, for example, an undulating pattern having peaks and troughs (e., sine, triangle, or ramp waves). In such cases, the undulating patterns of neighboring fins are out of phase, such that inter-fin contact during fin collapse is limited to peak/trough contact. In other embodiments, one or more ridges or nodules (short ridges), depending on the length of the fin, effectively limit the amount of inter-fin contact during fin collapse, such that only the ridges/nodules contact the neighboring fin.
    Type: Application
    Filed: December 30, 2016
    Publication date: February 27, 2020
    Applicant: INTEL CORPORATION
    Inventors: GLENN A. GLASS, CHYTRA PAWASHE, ANAND S. MURTHY, DANIEL PANTUSO, TAHIR GHANI
  • Patent number: 10457548
    Abstract: A conductive layer is deposited into a trench in a sacrificial layer on a substrate. An etch stop layer is deposited over the conductive layer. The sacrificial layer is removed to form a gap. In one embodiment, a beam is over a substrate. An interconnect is on the beam. An etch stop layer is over the beam. A gap is between the beam and the etch stop layer.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: October 29, 2019
    Assignee: Intel Corporation
    Inventors: Kevin Lai Lin, Chytra Pawashe, Raseong Kim, Ian A. Young, Kanwal Jit Singh, Robert L. Bristol
  • Publication number: 20190304784
    Abstract: Embodiments of the present disclosure describe techniques for reducing in-plane distortion from wafer to wafer bonding using a dummy wafer. One embodiment is an apparatus formed using a dummy wafer, the apparatus comprising: a device layer fusion bonded to a first side of a carrier wafer, wherein the dummy wafer comprises a first wafer and the carrier wafer comprises a second wafer that is different than the first wafer; wherein the device layer comprise a portion of a third wafer that is different than the second wafer; and wherein a second opposite side of the carrier wafer includes: a removal process artifact, wherein a distortion signature present in the portion of the second wafer is indicative of the use of the dummy wafer fusion bonded to the second side of the carrier wafer, or a remainder of the dummy wafer. Other embodiments may be disclosed and/or claimed.
    Type: Application
    Filed: April 2, 2018
    Publication date: October 3, 2019
    Inventors: Chytra PAWASHE, Daniel PANTUSO
  • Publication number: 20190148188
    Abstract: Micro pick-and-bond heads, assembly methods, and device assemblies. In, embodiments, micro pick-and-bond heads transfer micro device elements, such as (micro) LEDs, en masse from a source substrate to a target substrate, such as a LED display substrate. Anchor and release structures on the source substrate enable device elements to be separated from a source substrate, while pressure sensitive adhesive (PSA) enables device elements to be temporarily affixed to pedestals of a micro pick-and bond head. Once the device elements are permanently affixed to a target substrate, the PSA interface may be defeated through peeling and/or thermal decomposition of an interface layer.
    Type: Application
    Filed: December 18, 2018
    Publication date: May 16, 2019
    Applicant: Intel Corporation
    Inventors: Peter L. Chang, Chytra Pawashe, Michael C. Mayberry, Jia-Hung Tseng
  • Patent number: 10282965
    Abstract: Techniques are disclosed for using synthetic jet technology as an air delivery device for sensing applications. In particular, a synthetic jet device is used to deliver a controlled airflow or other fluidic flow to a sensor measurement area. Such a sensing system can be used to detect accurate concentration of target features present in the ambient surroundings, such as gases, particles, solutions, mixtures, and any other environmental features that can be sensed from a controlled airflow. An example application is air quality monitoring by using one or more synthetic jet devices to deliver a known or otherwise controlled airflow to a sensing area, thereby allowing for detection of harmful or otherwise unacceptable concentrations of particulate matter, gases, or air pollutants. In some embodiments, a synthetic jet device is operatively coupled with a sensor via a flow channel in a common housing, so as to provide a controlled flow sensing system.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: May 7, 2019
    Assignee: INTEL CORPORATION
    Inventors: Jessica Gullbrand, Melissa A. Cowan, Chytra Pawashe, Feras Eid
  • Patent number: 10242892
    Abstract: Micro pick-and-bond heads, assembly methods, and device assemblies. In, embodiments, micro pick-and-bond heads transfer micro device elements, such as (micro) LEDs, en masse from a source substrate to a target substrate, such as a LED display substrate. Anchor and release structures on the source substrate enable device elements to be separated from a source substrate, while pressure sensitive adhesive (PSA) enables device elements to be temporarily affixed to pedestals of a micro pick-and-bond head. Once the device elements are permanently affixed to a target substrate, the PSA interface may be defeated through peeling and/or thermal decomposition of an interface layer.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: March 26, 2019
    Assignee: Intel Corporation
    Inventors: Peter L. Chang, Chytra Pawashe, Michael C. Mayberry, Jia-Hung Tseng
  • Patent number: 10204808
    Abstract: Micro pick-and-bond heads, assembly methods, and device assemblies. In, embodiments, micro pick-and-bond heads transfer micro device elements, such as (micro) LEDs, en masse from a source substrate to a target substrate, such as a LED display substrate. Anchor and release structures on the source substrate enable device elements to be separated from a source substrate, while pressure sensitive adhesive (PSA) enables device elements to be temporarily affixed to pedestals of a micro pick-and-bond head. Once the device elements are permanently affixed to a target substrate, the PSA interface may be defeated through peeling and/or thermal decomposition of an interface layer.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: February 12, 2019
    Assignee: Intel Corporation
    Inventors: Peter L. Chang, Chytra Pawashe, Michael C. Mayberry, Jia-Hung Tseng
  • Patent number: 9947805
    Abstract: Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: April 17, 2018
    Assignee: Intel Corporation
    Inventors: Chytra Pawashe, Kevin Lin, Anurag Chaudhry, Raseong Kim, Seiyon Kim, Kelin Kuhn, Sasikanth Manipatruni, Rafael Rios, Ian A. Young
  • Publication number: 20180086627
    Abstract: A conductive layer is deposited into a trench in a sacrificial layer on a substrate. An etch stop layer is deposited over the conductive layer. The sacrificial layer is removed to form a gap. In one embodiment, a beam is over a substrate. An interconnect is on the beam. An etch stop layer is over the beam. A gap is between the beam and the etch stop layer.
    Type: Application
    Filed: June 22, 2015
    Publication date: March 29, 2018
    Inventors: Kevin LAI LIN, Chytra PAWASHE, Raseong KIM, Ian A. YOUNG, Kanwal Jit SINGH, Robert L. BRISTOL
  • Patent number: 9926193
    Abstract: Nanoelectromechanical (NEMS) devices having nanomagnets for an improved range of operating voltages and improved control of dimensions of a cantilever are described. For example, in an embodiment, a nanoelectromechanical (NEMS) device includes a substrate layer, a first magnetic layer disposed above the substrate layer, a first dielectric layer disposed above the first magnetic layer, a second dielectric disposed above the first dielectric layer, and a cantilever disposed above the second dielectric layer. The cantilever bends from a first position to a second position towards the substrate layer when a voltage is applied to the cantilever.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: March 27, 2018
    Assignee: Intel Corporation
    Inventors: Jorge A. Munoz, Dmitri E. Nikonov, Kelin J. Kuhn, Patrick Theofanis, Chytra Pawashe, Kevin Lin, Seiyon Kim
  • Publication number: 20170278733
    Abstract: Micro pick-and-bond heads, assembly methods, and device assemblies. In, embodiments, micro pick-and-bond heads transfer micro device elements, such as (micro) LEDs, en masse from a source substrate to a target substrate, such as a LED display substrate. Anchor and release structures on the source substrate enable device elements to be separated from a source substrate, while pressure sensitive adhesive (PSA) enables device elements to be temporarily affixed to pedestals of a micro pick-and-bond head. Once the device elements are permanently affixed to a target substrate, the PSA interface may be defeated through peeling and/or thermal decomposition of an interface layer.
    Type: Application
    Filed: October 17, 2014
    Publication date: September 28, 2017
    Inventors: Peter L. Chang, Chytra Pawashe, Michael C. Mayberry, Jia-Hung Tseng
  • Publication number: 20170158501
    Abstract: Nanoelectromechanical (NEMS) devices having nanomagnets for an improved range of operating voltages and improved control of dimensions of a cantilever are described. For example, in an embodiment, a nanoelectromechanical (NEMS) device includes a substrate layer, a first magnetic layer disposed above the substrate layer, a first dielectric layer disposed above the first magnetic layer, a second dielectric disposed above the first dielectric layer, and a cantilever disposed above the second dielectric layer. The cantilever bends from a first position to a second position towards the substrate layer when a voltage is applied to the cantilever.
    Type: Application
    Filed: June 27, 2014
    Publication date: June 8, 2017
    Applicant: Intel Corporation
    Inventors: Jorge A. MUNOZ, Dmitri E. NIKONOV, Kelin J. KUHN, Patrick THEOFANIS, Chytra PAWASHE, Kevin LIN, Seiyon KIM
  • Publication number: 20160329438
    Abstract: Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.
    Type: Application
    Filed: May 10, 2016
    Publication date: November 10, 2016
    Inventors: Chytra Pawashe, Kevin Lin, Anurag Chaudhry, Raseong Kim, Seiyon Kim, Kelin Kuhn, Sasikanth Manipatruni, Rafael Rios, Ian A. Young
  • Publication number: 20160171869
    Abstract: Techniques are disclosed for using synthetic jet technology as an air delivery device for sensing applications. In particular, a synthetic jet device is used to deliver a controlled airflow or other fluidic flow to a sensor measurement area. Such a sensing system can be used to detect accurate concentration of target features present in the ambient surroundings, such as gases, particles, solutions, mixtures, and any other environmental features that can be sensed from a controlled airflow. An example application is air quality monitoring by using one or more synthetic jet devices to deliver a known or otherwise controlled airflow to a sensing area, thereby allowing for detection of harmful or otherwise unacceptable concentrations of particulate matter, gases, or air pollutants. In some embodiments, a synthetic jet device is operatively coupled with a sensor via a flow channel in a common housing, so as to provide a controlled flow sensing system.
    Type: Application
    Filed: December 11, 2014
    Publication date: June 16, 2016
    Applicant: INTEL CORPORATION
    Inventors: Jessica Gullbrand, Melissa A. Cowan, Chytra Pawashe, Feras Eid
  • Patent number: 9362074
    Abstract: Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: June 7, 2016
    Assignee: Intel Corporation
    Inventors: Chytra Pawashe, Kevin Lin, Anurag Chaudhry, Raseong Kim, Seiyon Kim, Kelin Kuhn, Sasikanth Manipatruni, Rafael Rios, Ian A. Young