Display including an LED element having a pressure sensitive adhesive (PSA) for micro pick and bond assembly of the display
Micro pick-and-bond heads, assembly methods, and device assemblies. In, embodiments, micro pick-and-bond heads transfer micro device elements, such as (micro) LEDs, en masse from a source substrate to a target substrate, such as a LED display substrate. Anchor and release structures on the source substrate enable device elements to be separated from a source substrate, while pressure sensitive adhesive (PSA) enables device elements to be temporarily affixed to pedestals of a micro pick-and bond head. Once the device elements are permanently affixed to a target substrate, the PSA interface may be defeated through peeling and/or thermal decomposition of an interface layer.
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This Application is a Divisional of U.S. patent application Ser. No. 15/512,342, filed on 17 Mar. 2017, and titled “MICRO PICK AND BOND ASSEMBLY”, which is a National Stage Entry of, and claims priority to, PCT Application No. PCT/US14/61053, filed on 17 Oct. 2014 and titled “MICRO PICK AND BOND ASSEMBLY”, which is incorporated by reference in its entirety for all purposes.
BACKGROUNDIn contrast to conventional IC assemblies that integrate a number of IC chips or die having millimeter lateral chip dimensions onto a substrate, micro device assemblies integrate electronic and/or photonic devices having lateral chip dimensions in the micrometer regime (e.g., 1-10 μm). Die isolation, handling, bonding, and interconnection are all more of a challenge for micro device assemblies than conventional IC assemblies. For example, traditional pick-and-place methods can handle devices down to ˜200 μm in the lateral (XY) dimensions and 100 μm in thickness (Z). Due to this large chip thickness, it is difficult to form interconnects that allow miniaturization of the package.
Micro device assembly techniques under development include so-called transfer printing methods that have been shown capable of integrating into an assembly micro dice having lateral dimensions in the 10's of micrometers and ˜1 μm in Z thickness. One exemplary transfer printing technique relies on a sophisticated MEMS print head providing thousands of electrostatic clamping points. Another exemplary transfer printing technique relies on low temperature bonding with polydimethylsiloxane (PDMS), which is not compatible with high temperature chip bonding techniques, like solder bonding.
Electronic displays are one area that may benefit from advanced micro device assembly techniques. Electronic display technology has advanced rapidly in recent years as an important user interface to electronic devices. To date, liquid crystal display (LCD) technology has been the dominant display technology for both large format (e.g., television) and mobile devices. Current LCD based displays however only pass through μ5% of light from a backlight source (e.g., LED or CFL, etc.) leading to poor power efficiency, insufficient daylight display illumination, and poor viewing angles.
Considerable research and development has been expended on organic light emitting diode (OLED) display technology. OLED displays improve display power efficiency, though not dramatically, relative to LCD. OLED technology also currently suffers from color fading, leading to decreased display endurance/lifetime. Another next-gen display technology under investigation is crystalline LED, also referred to as inorganic LED (iLED). A crystalline LED display relies on an array of crystalline semiconductor LED chips. A crystalline LED display, for example, may utilize one LED chip for one picture element, or pixel. The power efficiency of crystalline LED is one order of magnitude more efficient than that of OLED, however a high volume manufacturing process has not been demonstrated for display applications. One of the technical challenges of crystalline LED is that a vast number of very small crystalline LEDs need to be transferred from a monolithic growth/fabrication medium into a spatially larger array electrically interconnected in a manner that enables controlled light emission. For current display resolutions (e.g., HD), one may expect hundreds of thousands of crystalline LED elements within a 1″ square of display area with each crystalline LED element on the micron scale (e.g., 5 μm, or less on a side).
Micro-bonding techniques capable of assembling crystalline LED displays are therefore advantageous.
The material described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements. In the figures:
One or more embodiments are described with reference to the enclosed figures. While specific configurations and arrangements are depicted and discussed in detail, it should be understood that this is done for illustrative purposes only. Persons skilled in the relevant art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of the description. It will be apparent to those skilled in the relevant art that techniques and/or arrangements described herein may be employed in a variety of other systems and applications other than what is described in detail herein.
Reference is made in the following detailed description to the accompanying drawings, which form a part hereof and illustrate exemplary embodiments. Further, it is to be understood that other embodiments may be utilized and structural and/or logical changes may be made without departing from the scope of claimed subject matter. It should also be noted that directions and references, for example, up, down, top, bottom, and so on, may be used merely to facilitate the description of features in the drawings. Therefore, the following detailed description is not to be taken in a limiting sense and the scope of claimed subject matter is defined solely by the appended claims and their equivalents.
In the following description, numerous details are set forth. However, it will be apparent to one skilled in the art, that embodiments of the present invention may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring embodiments of the present invention. Reference throughout this specification to “an embodiment” or “one embodiment” means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase “in an embodiment” or “in one embodiment” in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.
As used in the description and the appended claims, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
The terms “coupled” and “connected,” along with their derivatives, may be used herein to describe functional or structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. “Coupled” may be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship).
The terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example in the context of materials, one material or material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials or materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material or material “on” a second material or material is in direct contact with that second material/material. Similar distinctions are to be made in the context of component assemblies.
As used in the description, and in the claims, a list of items joined by the term “at least one of” or “one or more of” can mean any combination of the listed terms. For example, the phrase “at least one of A, B or C” can mean A; B; C; A and B; A and C; B and C; or A, B and C. Described herein are micro pick and bond assembly techniques, micro pick-and-bond (μPnB) assembly equipment, and micro device assemblies. In contrast to known transfer printing methods, μPnB methods can integrate micro-devices without the complexity of high voltage electrostatic heads, and are compatible with high temperature solder bonding. In embodiments, micro pick-and-bond heads transfer micro device elements, such as (micro) LEDs, en masse from a source substrate to a target substrate, such as a LED display substrate. Anchor and release structures on the source substrate enable device elements to be separated from a source substrate, while pressure sensitive adhesive (PSA) enables device elements to be temporarily affixed to pedestals of a micro pick-and bond head. Once the device elements are permanently affixed to a target substrate, the PSA interface may be defeated through peeling and/or thermal decomposition of an interfacial material. The μPnB heads and assembly techniques described herein are particularly advantageous for integrating hundreds of thousands to many millions of micro devices onto an assembly substrate, for example to assemble a μLEDs into a display.
In certain exemplary embodiments described further below, a μPnB assembly head is completely passive, having no electrical components or circuitry, such as electrodes. A purely mechanical μPnB assembly head has the advantage of being less complex than electrically controlled heads such as those employing electrostatic force to pick up micro dice. In contrast to an electrostatic head, a passive μPnB assembly head in accordance with one or more embodiment described herein lacks electrostatic clamping electrodes. There is therefore no need for active high voltage control, and no need to build up and bleed off an image charge in each of the die during the assembly process.
A number of μPnB assembly embodiments are described in detail below in the context of μLEDs and μLED displays. It is noted however that the various features of μPnB exemplified with the μLED embodiments for the sake of consistency and clarity of description may be readily applied to any micro device electronic, photonic, or otherwise (e.g., MEMS).
In an embodiment, the source substrate received at operation 105 includes a plurality of devices, each including a device stack that has been fabricated at a wafer-level with some nominal source substrate device pitch. One or more of the devices in the source substrate are to be picked up and bonded to the target substrate, for example at some target substrate device pitch that may be an integer multiple of the source substrate device pitch to reduce wasted space on the source substrate.
Referring first to
Source substrate 201A further includes crystalline LED elements 230 anchored to carrier 220. LED elements 230 may be rectangular (e.g., square) or patterned to have alternative shapes (e.g., a circular footprint). Each element 230 includes a LED film stack 207. Generally, any known semiconductor LED film stack may be utilized. In embodiments, LED film stack 207 includes one or more semiconductor heterojunction(s), for example forming a quantum well, etc. Semiconductor LED film stack 207 includes at least two complementary doped semiconductor regions (layers): a p-type doped layer and an n-type doped layer in a diodic stack architecture. In specific embodiments, semiconductor LED film stack 207 is a heteroepitaxial III-N semiconductor film stack, for example comprising GaN and/or alloys thereof, such as InGaN. The composition of semiconductor LED film stack 207 however is dependent on the desired emission band, and embodiments herein are not limited in that respect.
Each LED element 230 further includes an electrode metal 210 contacting the LED film stack. The composition of electrode metal 210 may vary as a function of the LED film stack, for example to provide a desired metal work function suitable for providing an ohmic contact, tunneling contact, etc. In one exemplary embodiment, metal 210 is a p-type metal suitable for making contact to p-type doped semiconductor layer of an LED film stack. Each LED element 230 further includes a second metal electrode 225 contacting the LED film stack. The composition of second electrode metal 225 may vary as a function of the LED film stack, for example to provide a desired metal work function suitable for providing an ohmic contact, tunneling contact, etc. In one exemplary embodiment, metal 225 is an n-type metal suitable for making contact to n-type doped semiconductor layer of an LED film stack.
Adjacent LED elements 230 are separated by trenches etched into the LED semiconductor film stack. The dimensions/pitch of the trenches substantially set the dimensions of the LED elements that will be incorporated into a display assembly. As illustrated in
In exemplary embodiments, the lateral element width We of each LED element 230 is patterned to be no more than 5 μm. In advantageous embodiments, the thickness of the dielectric material utilized for spacer formation is selected to ensure dielectric spacer 235 has a lateral thickness, or width Ws that is less than half the nominal lateral width Wt of the trenches 232 etched into the LED film stack at operation 935 (
LED elements 230 are anchored to carrier 220 for a controlled release of the LED elements 230 from carrier 220. The LED element anchors are formed within the trenches between adjacent elements, for example intersecting portions of the LED element sidewalls while still leaving access for a release agent to undercut the LED elements. Anchor material may be back filled into the trenches, planarizing with a top surface of LED elements 230, for example with a spin-on process. The planarized anchor material may then be recessed below the top surface of LED and/or patterned into a plurality of separate anchors. The recessed anchors avoid contamination to the μPnB head during pick up and further allow reduction of anchoring strength to ease the pickup. In one advantageous embodiment, the anchor material is a photosensitive polymeric material (e.g., photoresist) spin-coated into the trenches. Resist recess can be accomplished with well-known techniques such as a blanket ashing (both positive and negative resists), image reversal (positive resist) or a blanket development (negative resist). The photoresist is then lithographically patterned (i.e., exposed and developed) into separate LED element anchors 245 filling the trench and maintaining separation between adjacent LED elements 230 as further illustrated in
In the alternative embodiment illustrated in
Returning to
Referring first to
Disposed over the carrier 305 is a display backplane interface having first metal interconnects that are to interface a first LED electrode with a display blackplane (e.g., driving circuitry, access transistors, and/or discrete electronics, etc.). In the exemplary embodiment illustrated in
In embodiments, a μPnB target substrate has lands that include a solder feature or a conductive adhesive element. Target substrate 301A illustrates a conductive adhesive 350 applied to metal interconnect 340. Conductive adhesive 350 is to receive an LED element, affix the LED element to the bonding target substrate while the LED display assembly is built up around the LED element. In the exemplary embodiment, conductive adhesive 350 is to electrically connect one of the metal interconnects 340 to a metal electrode on a first (back) side of an LED element. In one advantageous embodiment, the conductive adhesive is a structural adhesive such as a photosensitive conductive film (e.g., a conductive photoresist). An example of such material is a photoresist (e.g., SU-8 25) doped with a conductive polymer (e.g., polyaniline). Some conductive photoresist formulations have been described in technical literature as having a resistivity in the range of 1 ohm-cm. At this resistivity, parasitic electrical resistance attributable to the conductive polymer of around 0.5 μm thick, employed in accordance with embodiments herein is expected to be in the range of ˜200 ohms for a 5×5 μm LED element. This resistance is much smaller than typical (p-type) contact resistance (e.g., >2 kohm) for an element of this size. Patterning and alignment of the conductive polymer elements is non-critical. For an exemplary 10 μm metal interconnect pad, the conducting polymer element may have a lateral dimension of 10-15 μm on a 25 μm pitch.
In another embodiment also illustrated in
In an embodiment, a μPnB target substrate further includes at least one mechanical stand-off adjacent a die land. Such stand-offs need not be adjacent to every die land on a source substrate, and may for example be distributed sparsely over the target substrate with enough density to ensure planar engagement between the μPnB head and the target substrate.
In another embodiment, an optically transmissive adhesive is employed to affix the die to the target substrate. Referring to
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In another embodiment, a sacrificial material interfacing the PSA material is decomposed to break the PSA bond between die and the μPnB head pedestals. In advantageous embodiments, the sacrificial interface material is present on the die-side of the PSA material. This enables the PSA material to remain on the μPnB head pedestals for reuse during a subsequent iteration of method 101. As one example, the sacrificial interface material is a thermally decomposable material pre-applied to the die. The thermally decomposable material may be thermally decomposed at operation 135. As described further below, polycarbonate is one example of a thermally decomposable material that may be utilized to effect separation between μPnB head pedestals and the die at temperatures of 250° C., or more. In one such embodiment, an elevated temperature employed at the bonding operation 130 is insufficient to decompose the thermally decomposable material (e.g., <250° C.), but is sufficient to form a solder alloy (e.g., >160° C.) that has a (re)melt temperature (e.g., >350° C.) above the thermal decomposition temperature of the thermally decomposable interface material. Once the high melt temperature alloy is formed at operation 130 (e.g., at 180-200° C.), operation 135 may entail heating to a higher temperature (e.g., 250-300° C.) to thermally decompose the sacrificial material.
The μPnB assembly method 101 may then be iterated through the pickup and bonding operations described above until a die (e.g., LED element) is bonded to all lands on the target substrate. After attaching all source dice to the target substrate, the target substrate may be further processed to complete interconnection and/or encapsulation of the micro devices assembled onto the target substrate. Any assist structures (e.g., standoffs 333) fabricated on the target substrate to facilitate μPnB assembly may also be removed.
Notably, successful execution of μPnB assembly method 101 depends, at least in part, on the source and target substrates having sufficient flatness, and/or the μPnB assembly head having sufficient flatness. In advantageous embodiments, the μPnB assembly head includes microtools capable of accommodating a threshold level of non-planarity between the μPnB assembly head pedestals and the target substrate.
Referring first to
The μPnB assembly tool 601 may be built up by operating any known pick-n-place/compression die bonder to first pick up μPnB assembly head 401. The μPnB assembly head 401 is to be successively placed on a bonding source substrate and a bonding target substrate to transfer a plurality of micro die between the source and target substrates with each iteration. When μPnB assembly head 401 is placed on the bonding source substrate, microtools on head 401 temporary bond with the source die (e.g., with PSA material) to defeat the source substrate anchoring. When bonder 655 (re)places the μPnB assembly head 401 onto the bonding target substrate, the permanent bond formed between the die and target defeat the temporary bond with the μPnB assembly head 401. Then bonder 655 (re)places the μPnB assembly head 401 onto the bonding source substrate for another μPnB iteration. In the event μPnB assembly head 401 becomes aged, (e.g., after one or more placements between bonding source and target substrates), bonder 655 drops the aged μPnB assembly head 401 between micro die μPnB iterations and picks up a replacement μPnB assembly head 401 from a μPnB head tray. In this manner, μPnB assembly head 401 interacts with compression bonder 655 much like any millimeter-scale die. However, once picked up by bonder 655, the μPnB assembly head 401 serves as further tooling enabling compression bonder 655 to perform a μPnB assembly method (e.g., μPnB assembly method 101).
Referring again to
At operation 615, PSA material is deposited over the substrate (e.g., over the head assembly material stack). The PSA material may be any known material that has a peel force suitable for the application (e.g., <1 N/cm). In further embodiments where the PSA material is to withstand high temperature die bonding, the PSA material is also stable at high temperatures. For example, the PSA material may be silicone-based (e.g., a siloxane polymer), as described above. In advantageous embodiments the PSA material is applied by spin-coating a silicone-based polymer mixture onto the head substrate and then curing and/or drying the mixture into the PSA material layer.
Returning to
Although in the exemplary embodiment depicted, PSA material layer 731 has substantially the same lateral dimensions as dielectric base layer 723 (i.e., nearly vertical pedestal sidewalls), in alternative embodiments pedestal 741 may be thick (e.g., 5 μm instead of 1 μm) and patterned to have positively sloped sidewalls with the PSA material layer 731 having a smaller lateral dimension than that of the dielectric base layer 723 to improve pedestal compliance. In still other embodiments, dielectric base material 723 has a bi-layer structure and a first layer of the bi-layer dielectric base material is undercut laterally relative to the second layer of the dielectric base material. For example a bottom layer of the bi-layer base material may be undercut by an amount equal to at least 10%-30% of the lateral width of the second layer of the bi-layer dielectric. An example of pedestal undercut is illustrated with dashed line in
Returning to
In an embodiment, fabrication of each flexural member at operation 630 entails etching a portion of the low stress layer and etching a recess in the substrate that undercuts the flexural member below the pedestal. The flexural member then extends over the recess allowing deflection of the flexural member in a direction perpendicular to the substrate surface.
Following the patterning, many polyimide materials require high temperature curing. In some embodiments, where the curing temperature may be too high for PSA 731, PI is instead cured prior to depositing layers 727 and 731. The cured PI may then be dry etched after the removal of layers 727 and 731 instead of the flood exposure described above. In the exemplary embodiment illustrated in
As noted above, in some embodiments, a sufficiently thick PSA layer 731 alone provides adequate compliance for sufficiently planar source and target substrates and complexities associated with the flexural member may be avoided. For such embodiments, the microtool 380 includes just the pedestal 741 without any underlying flexural member. In certain such embodiments, substrate 805 may be a regular crystalline silicon wafer without the device layer 821 and the intervening dielectric layer 718.
In embodiments, the μPnB source substrate includes a PSA material. PSA material may be incorporated into the source substrate in addition to, or in the alternative to, incorporation of PSA material into a μPnB assembly head.
Method 901 entails wafer-level processing suitable for generating the LED source substrate from a semiconductor LED film stack received at operation 905. The semiconductor LED film stack may be a contiguous film covering an epitaxial substrate to form a monolithic body (e.g., an LED epi wafer). Generally, any known semiconductor LED film stack may be utilized. In the exemplary embodiment illustrated in
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At operation 940, a dielectric sidewall spacer is formed over the LED element sidewalls. Any known dielectric material, such as but not limited to amorphous Si or carbon, SiOx, SiON, SiN, CDO, and CDN may be conformally deposited over the LED elements. An anisotropic etch is then performed using any anisotropic etch process known in the art to be suitable for the chosen dielectric material to form an at least partially self-aligned sidewall coating over the metal and semiconductor sidewalls of each LED element.
Bonding material 1012 may then be removed to release the LED elements except for selected anchor points, or if the bonding material is a PSA material, the LED elements may be removed from the source substrate simply by overcoming the bonding material coupling the elements to the carrier. For example the PSA material coupling the elements to the carrier may be selected to have a lower peel strength and/or lower shear strength relative to the PSA material on a topside of the LED elements at operation 930 (
Alternatively, LED element anchors may be patterned within the trenches between adjacent elements and the bonding material layer 1012 removed around the anchor. For such an embodiment, the bonding material layer 1012 may be an adhesive or otherwise (SiOx). As further illustrated in
Anchors 245 landing on carrier 220 are then surrounded by a free-space void 249 extending over the entire lateral area or footprint of each LED element 230. In the exemplary embodiments where a photosensitive polymer is employed for the anchor material, each anchor 245 is a polymer pillar contacting the sidewall dielectric (spacer 235) coating at least two adjacent LED elements 230 (e.g., four nearest LED elements 230 are connected by each anchor 245 located at corners of elements 230, or two nearest LED elements are connected if anchors 245 are located at edges instead of the corners). Capping material 1035 is then removed to expose PSA material 1027. Source substrate 1050 illustrated in
Method 1101 begins with receiving a plurality of monolithically integrated LED elements disposed over a carrier substrate at operation 1105. In the exemplary embodiment, the LED elements have been fabricated on an epitaxial substrate and transferred to the carrier substrate substantially as described above in the context of operations 905-920 (
LED displays assembled in accordance with embodiments herein may be incorporated into an electronic device embodied in varying physical styles or form factors.
As shown in
While certain features set forth herein have been described with reference to various implementations, this description is not intended to be construed in a limiting sense. Hence, various modifications of the implementations described herein, as well as other implementations, which are apparent to persons skilled in the art to which the present disclosure pertains are deemed to lie within the spirit and scope of the present disclosure.
It will be recognized that the inventive scope is not limited to the embodiments so described, but can be practiced with modification and alteration without departing from the scope of the appended claims. For example the above embodiments may include specific combinations of features as further provided below.
In one or more first embodiment, a micro-pick-and-bond (μPnB) assembly head comprises a substrate, a plurality of pedestals. Each pedestal comprises a base mechanically coupled to the substrate and a pressure sensitive adhesive (PSA) material at a tip opposite the substrate.
In furtherance of the first embodiment, the assembly head further comprising a plurality of flexural members arrayed over the substrate, each pedestal coupled to the substrate through one or more of the flexural members.
In furtherance of the first embodiment, the base comprises a dielectric material disposed between the PSA material and the flexural member.
In furtherance of the first embodiment, a largest lateral dimension of the pedestal base is less than 10 μm, and a height of the pedestal from the flexural member is less than 10 μm.
In furtherance of the first embodiment, the PSA material has sloped sidewalls with the PSA having lateral dimensions proximal to the tip being smaller than those proximal to the substrate, and/or the base comprises a dielectric material disposed between the PSA material and the substrate and a portion of the dielectric base material is undercut with the area the dielectric base layer proximal to the substrate being less than the area of an exposed surface the adhesive material.
In furtherance of the first embodiment, the PSA material is a silicone-based PSA material; and the pedestal base comprises a polymeric dielectric material.
In furtherance of the first embodiment, the PSA material is stable to at least 160° C.
In furtherance of the embodiment immediately above, the PSA material is stable to at least 250° C., and comprises a siloxane polymer.
In furtherance of the first embodiment, each flexural member is elastically deformable by at least 0.1 μm in a direction perpendicular to the substrate surface.
In furtherance of the embodiment immediately above, each flexural member has a spring constant of 100-600 N/m, and the PSA material has a peel strength of no more than 1.0 N/cm.
In furtherance of the embodiment above, each flexural member extends over a recess in the substrate surface, and the pedestal is coupled to a region of the flexural member between anchoring points that contact the substrate surface.
In furtherance of the embodiment immediately above, the flexural member comprises at least one metal thin film or semiconductor thin film anchored to the substrate by a dielectric thin film material.
In furtherance of the first embodiment, the substrate comprises glass or crystalline silicon having a site flatness of less than 1 μm for an 8×25 mm site, and the flexural member comprises a crystalline silicon layer of the substrate or a metal thin film separated from the substrate by a stoichiometric SiO2 layer.
In furtherance of the first embodiment, the pedestal has a circular top surface with a diameter less than 5 μm.
In one or more second embodiment, a crystalline LED display, comprises a display interface including a plurality of metal interconnects, and a plurality of LED elements. Each of the plurality of LED elements include a first metal electrode coupled to at least one of the metal interconnects, and at least one of the plurality of LED elements further includes a pressure sensitive adhesive (PSA) over a surface of the LED element opposite the first metal electrode.
In furtherance of the first embodiment, the PSA comprises a siloxane polymer, and the metal interconnect is coupled to the first electrode by solder or conductive adhesive.
In one or more third embodiment, a method of fabricating a micro-pick-and-bond (μPnB) assembly head include depositing a pressure sensitive adhesive (PSA) material layer over a substrate, and patterning the PSA material layer into a plurality of pedestals arrayed over the substrate.
In furtherance of the third embodiment, the method further includes depositing a dielectric base layer over a low stress material layer disposed on a substrate. The method comprises depositing a pressure sensitive adhesive (PSA) material layer over the dielectric base layer. The method comprises patterning the PSA material layer and the dielectric base layer into a plurality of pedestals. The method comprises patterning the low stress material layer into a plurality of flexural members, each flexural member structurally supporting at least one of the pedestals. The method comprises forming a recess in the substrate that undercuts the flexural member below the pedestal.
In furtherance of the third embodiment, depositing the dielectric base layer further comprises spin coating a mixture including a high temperature stable polymer over the low stress material and curing or drying the mixture into the dielectric base layer. Depositing the PSA material layer further comprises spin coating a liquid mixture including a siloxane polymer and curing or drying the mixture into the PSA material layer. Patterning the PSA material layer and the dielectric base layer into a plurality of pedestals further comprises depositing and patterning a photoresist over the PSA material layer, and etching or dissolving portions of the PSA material layer and dielectric base layer unprotected by the patterned photoresist.
In furtherance of the third embodiment, the method further comprises depositing an inorganic dielectric material between the dielectric base layer and the pressure sensitive adhesive (PSA) material and patterning the inorganic dielectric material along with the PSA material and the dielectric base layer to form the pedestals. The method further comprises reducing an area of the interface between the dielectric base layer and the flexural member to less than an exposed surface area of the PSA material by undercutting the dielectric base layer.
In one or more fourth embodiment, a micro-pick-and-bond (μPnB) assembly method, comprises aligning a plurality of μPnB head pedestals with a plurality of die anchored to a source substrate. The method comprises pressing each the plurality of die with a surface of at least one of the μPnB head pedestals to adhere a die to a pedestal with a pressure sensitive adhesive (PSA) material. The method comprises breaking anchors between the die and the source substrate by displacing the μPnB head pedestals relative to the source substrate while the die are adhered to the pedestals with the PSA material. The method comprises aligning the plurality of die affixed to the μPnB head pedestals with lands on a bonding target substrate. The method comprises affixing the plurality of die to the lands on the bonding target substrate. The method comprises breaking the PSA bond between the die and the pedestals while the die are affixed to the lands.
In furtherance of the embodiment immediately above, breaking the PSA bond between the die and the pedestals further comprises at least one of displacing the μPnB head pedestals relative to the target substrate, or thermally decomposing a thermally decomposable material interfacing the PSA material.
In furtherance of the embodiment immediately above, breaking the PSA bond between the die and the pedestals further comprises displacing the μPnB head pedestals in both lateral and vertical directions concurrently to peel the PSA material from an interface material of either the pedestal or the die.
In furtherance of the fourth embodiment, affixing the plurality of die to the lands on the bonding target substrate further comprises solder bonding the die.
In one or more fifth embodiment, a micro-pick-and-bond (μPnB) source substrate comprises a carrier, and a plurality of device elements disposed over the carrier. Each device element further comprises a device material stack, an electrode between the device material stack and the carrier, and at least one of a pressure sensitive adhesive (PSA) material or a thermally decomposable material separated from the electrode by at least the device material stack.
In furtherance of the fifth embodiment, the plurality of device elements comprises a plurality of LED elements. Each LED element further comprises a semiconductor LED film stack including at least first and second doped semiconductor regions disposed between a first metal LED electrode and a second metal LED electrode, the first metal LED electrode facing the carrier and spaced apart from the carrier by a free-space void. Each LED element further comprises a sidewall dielectric coating disposed over sidewalls of the LED film stack, the first metal LED electrode, and the second metal LED electrode. The source substrate further comprises a plurality of anchors disposed within trenches separating each LED element from adjacent LED elements.
In furtherance of the fifth embodiment, the plurality of device elements comprises a plurality of LED elements. Each LED element further comprises an epitaxial semiconductor LED film stack including at least first and second doped semiconductor regions, a first metal LED electrode in contact with the first doped semiconductor region, a dielectric sidewall spacer around the first metal LED electrode and a sidewall of the first doped semiconductor region, and a second metal LED electrode further comprising a metal spacer adjacent to the dielectric spacer and in electrical contact with the second doped semiconductor region. The source substrate further comprises a plurality of anchors disposed within trenches separating each LED element from adjacent LED elements.
In one or more sixth embodiment, a method of forming a micro-pick-and-bond (μPnB) source substrate comprises monolithically fabricating a plurality of microelectronic or photonic devices on a substrate. The method comprises applying a pressure sensitive adhesive (PSA) over the monolithic microelectronic or photonic devices. The method comprises patterning trenches through the PSA and between the microelectronic or photonic devices to define individual die. The method comprises releasing the individual die from the substrate by etching one or more material surrounding one or more anchor coupled to each die.
In furtherance of the sixth embodiment, monolithically fabricating the plurality of microelectronic or photonic devices on the substrate further comprises forming a device material stack over a first substrate, performing a substrate-level transfer of the device material stack from the first substrate to a carrier substrate, and applying the PSA over the device material stack while affixed to the carrier substrate.
In furtherance of the embodiment immediately above, performing the substrate-level transfer further comprises applying a second PSA material to at least one of the carrier and the surface of the device material stack, compressing the second PSA material between carrier and the device material stack, and removing the first substrate to expose the device material stack. Releasing the individual die from the substrate by etching one or more material surrounding one or more anchor coupled to each die further comprises dissolving the second PSA material between the carrier and the device material stack.
In furtherance of the embodiment immediately above, the carrier comprises and electrostatic carrier with one or more electrostatic clamping structure. Compressing the PSA material between carrier and the device material stack comprises applying a voltage to the electrostatic carrier to develop an electric field across the PSA material.
In furtherance of the sixth embodiment, monolithically fabricating the plurality of microelectronic or photonic devices on the substrate further comprises depositing a first metal electrode film over a semiconductor LED film stack covering an epitaxial substrate. Monolithically fabricating the plurality of microelectronic or photonic devices on the substrate further comprises transferring the LED film and electrode stack to a carrier, the first metal electrode film facing the carrier. Monolithically fabricating the plurality of microelectronic or photonic devices on the substrate further comprises depositing a second metal electrode film over the LED film stack. Monolithically fabricating the plurality of microelectronic or photonic devices on the substrate further comprises forming a plurality of LED elements by etching trenches into the LED film stack, first metal electrode film, and the second metal electrode film, each LED element having sidewalls defined by the trench etching. Monolithically fabricating the plurality of microelectronic or photonic devices on the substrate further comprises forming dielectric spacer over LED element sidewalls. Monolithically fabricating the plurality of microelectronic or photonic devices on the substrate further comprises forming LED element anchors within the trenches, the anchors intersecting portions of the LED element sidewalls. Monolithically fabricating the plurality of microelectronic or photonic devices on the substrate further comprises releasing the LED elements from the carrier except for the anchors by laterally etching a release layer between the LED element and the carrier.
In one or more seventh embodiment, a micro-pick-and-bond (μPnB) target substrate comprises a plurality of die lands arrayed over the target substrate, each die land further comprising solder or an adhesive, and at least one mechanical stand-off adjacent to at least one of the die lands, the standoff having a z-height greater than a z-height of the die land added to a z-height of a die to be affixed to the land.
In furtherance of the seventh embodiment, the standoff comprises photoresist.
In furtherance of the seventh embodiment, each die land comprises an optically transmissive adhesive or a conductive adhesive.
However, the embodiments are not limited to the examples above, and in various implementations the above embodiments may include the undertaking only a subset of such features, undertaking a different order of such features, undertaking a different combination of such features, and/or undertaking additional features than those features explicitly listed. The inventive scope should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
Claims
1. A LED display, comprising:
- a display interface including a plurality of metal interconnects; and
- a plurality of LED elements, each comprising crystalline semiconductor, wherein: each of the plurality of LED elements includes: a first electrode coupled to a first of the metal interconnects; a LED material stack including at least first and second doped semiconductor regions over the first electrode; and a sidewall dielectric in direct physical contact with, and encircling, an outer perimeter sidewall of at least the LED material stack; and each the plurality of LED elements further includes a pressure sensitive adhesive (PSA) over at least a portion of a top surface of the LED element opposite the first electrode, the PSA having an outer perimeter sidewall also encircled by, and in direct physical contact with, the sidewall dielectric.
2. The LED display of claim 1, wherein the PSA comprises at least Si and oxygen.
3. The LED display of claim 2, wherein the PSA comprises a siloxane polymer.
4. The LED display of claim 1, wherein the first of the metal interconnects is coupled to the first electrode by solder or conductive adhesive.
5. The LED display of claim 4, wherein the first of the metal interconnects is coupled to the first electrode by conductive adhesive, and wherein the conductive adhesive comprises polyaniline.
6. The LED display of claim 5, wherein the conductive adhesive has a resistivity of not more than 1 ohm-cm.
7. The LED display of claim 4, wherein the display interface comprises a display backplane and the first of the metal interconnects couples the first electrode with one or more of display driving circuitry, access transistors, or discrete electronics.
8. The LED display of claim 7, wherein each of the plurality of LED elements has a dimension no more than 5×5 μm, wherein the first of the metal interconnects comprises a metal pad with a lateral dimension no larger than 10 μm and having a pitch with a second of the metal interconnects that is not over 25 μm.
9. The LED display of claim 1, further comprising:
- at least one mechanical stand-off adjacent to at least one of the LED elements, the standoff having a z-height greater than a z-height of one of the LED elements summed with a z-height of a die land to which the one of the LED elements is affixed.
10. The LED display of claim 1, wherein a top surface of the PSA is above a height of the sidewall dielectric.
11. The LED display of claim 1, wherein the PSA is in direct contact with at least a portion of a second electrode coupled to the LED material stack.
12. A LED display, comprising:
- a display interface including a plurality of metal interconnects; and
- a plurality of LED elements, each comprising crystalline semiconductor, wherein: each of the plurality of LED elements includes a first electrode coupled to a first of the metal interconnects through an optically transmissive adhesive; a LED material stack including at least first and second doped semiconductor regions over the first electrode; and a sidewall dielectric in direct physical contact with, and encircling, an outer perimeter sidewall of at least the LED material stack; and each of the plurality of LED elements further includes a pressure sensitive adhesive (PSA) over at least a portion of a top surface of the LED element opposite the first electrode, the PSA having an outer perimeter sidewall also encircled by, and in direct physical contact with, the sidewall dielectric.
13. The LED display of claim 12, wherein each of the LED elements is to emit light through the optically transmissive adhesive.
14. The LED display of claim 13, wherein the metal interconnects are between individual ones of the LED elements and a display cover.
15. The LED display of claim 14, wherein display cover comprises glass or sapphire.
16. The LED display of claim 12, wherein the PSA comprises at least Si and oxygen.
17. The LED display of claim 16, wherein the PSA comprises a siloxane polymer.
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Type: Grant
Filed: Dec 18, 2018
Date of Patent: Jan 5, 2021
Patent Publication Number: 20190148188
Assignee: Intel Corporation (Santa Clara, CA)
Inventors: Peter L. Chang (Portland, OR), Chytra Pawashe (Portland, OR), Michael C. Mayberry (Beaverton, OR), Jia-Hung Tseng (Portland, OR)
Primary Examiner: Robert T Huber
Assistant Examiner: Laura M Dykes
Application Number: 16/224,550
International Classification: H01L 21/67 (20060101); H01L 23/00 (20060101); H01L 33/00 (20100101); H01L 21/683 (20060101); H01L 25/075 (20060101); H01L 33/36 (20100101); H01L 33/44 (20100101); H01L 33/62 (20100101);