Abstract: Multiple termination impedance values are provided in a switchable termination circuit so as to accommodate multiple transmission line characteristics. In one example, a termination matching circuit includes first and second nodes, a series interconnection of a first switch and a first impedance coupled between the first and second nodes, and another series interconnection of a second switch and a second impedance coupled between the first and second nodes. First and second control circuits respectively control the first and second switches such that a selectable impedance is provided between the first and second nodes through selective activation of the first and second switch devices by the first and second control circuits. In another example, additional nodes and resistors are provided to provide further termination impedance values.

Abstract: Multiple termination impedance values are provided in a switchable termination circuit so as to accommodate multiple transmission line characteristics. In one example, a termination matching circuit includes first and second nodes, a series interconnection of a first switch and a first impedance coupled between the first and second nodes, and another series interconnection of a second switch and a second impedance coupled between the first and second nodes. First and second control circuits respectively control the first and second switches such that a selectable impedance is provided between the first and second nodes through selective activation of the first and second switch devices by the first and second control circuits. In another example, additional nodes and resistors are provided to provide further termination impedance values.

Abstract: A maximum voltage selection circuit may include multiple inputs, each for receiving a different input voltage, an output for delivering the highest of the input voltages, and a voltage selection circuit. The voltage selection circuit may automatically select the input having the largest voltage magnitude, automatically deliver the voltage at the selected input to the output, and not draw quiescent operating current from any of the inputs.

Abstract: A maximum voltage selection circuit may include multiple inputs, each for receiving a different input voltage, an output for delivering the highest of the input voltages, and a voltage selection circuit. The voltage selection circuit may automatically select the input having the largest voltage magnitude, automatically deliver the voltage at the selected input to the output, and not draw quiescent operating current from any of the inputs.

Abstract: A maximum voltage selection circuit may include multiple inputs, each for receiving a different input voltage, an output for delivering the highest of the input voltages, and a voltage selection circuit. The voltage selection circuit may automatically select the input having the largest voltage magnitude, automatically deliver the voltage at the selected input to the output, and not draw quiescent operating current from any of the inputs.

Abstract: An integrated system and method to achieve ESD robustness on an integrated circuit (IC) in a fully automated ASIC design environment is described. Electrical characteristics and electrical limits on the power network are translated to power route region constraints for each chip input/output (I/O) cell. Electrical limits on the signal network are translated into signal route region constraints for each chip I/O cell. These constraints are passed on to an I/O floorplanner (automatic placer of I/O cells) that analyzes trade-offs between these constraints. For I/O cells that can not be placed to satisfy both power and signal region constraints, the I/O floorplanner utilizes the knowledge of alternative power distribution structures to group I/Os and create local power grid structures that have the effect of relaxing the power region constraints. Instructions for creating these local power grid structures are passed on to the automatic power routing tool.

Abstract: A system and method of electrostatic discharge (ESD) protection in a logic circuit using either state manipulation or current injection. A first system is disclosed that includes an ESD detection circuit for detecting an ESD event; and an ESD control circuit that can change a state of the logic circuit from a normal mode to an ESD mode in response to a signal received from the ESD detection circuit. A second system is disclosed that includes an attenuator circuit coupled to a chip pad; and a switch for diverting current from the attenuator circuit to an internal node of the logic circuit during an ESD event to reduce a voltage at the chip pad.

Abstract: A method of manufacturing a device having embedded memory including a plurality of memory cells. During manufacturing test, a first test stress is applied to selected cells of the plurality of memory cells with a built-in self test. At least one weak memory cell is identified. The at least one weak memory cell is repaired. A second test stress is applied to the selected cells and the repaired cells with the built-in self test.

Abstract: A method for placing electrostatic discharge clamps within integrated circuit devices is disclosed. A region is initially defined within an integrated circuit design. A list of ESD-susceptible circuits located within the defined region is then generated. The center of gravity of the ESD-susceptible circuits located within the defined region is located. Next, an ESD protection device is placed at the center of gravity of the ESD-susceptible circuits located within the defined region. A determination is made as to whether or not all ESD-susceptible circuits within the list of ESD-susceptible circuits are protected by the placement of the ESD protection device. If so, the process is repeated in other regions until the entire integrated circuit is addressed. Otherwise, the defined region is divided into at least two smaller regions and the process is repeated.

Abstract: A method for sensing data stored within a cross point magnetic random access memory (MRAM) device includes establishing an offset voltage of a sense amplifier, the sense amplifier selectively coupled to a selected bitline within the MRAM device, the selected bitline being in communication with an MRAM cell to be read. A read current is applied through the MRAM cell to be read, and a reference current is applied through the selected bitline. A signal voltage is sensed on the selected bitline, the signal voltage being generated in response to the read current and the reference current. The signal voltage is coupled to an input of the sense amplifier, wherein the sense amplifier provides an offset corrected output reflective of the data state of the MRAM cell.

Abstract: A method for sensing data stored within a cross point magnetic random access memory (MRAM) device includes establishing an offset voltage of a sense amplifier, the sense amplifier selectively coupled to a selected bitline within the MRAM device, the selected bitline being in communication with an MRAM cell to be read. A read current is applied through the MRAM cell to be read, and a reference current is applied through the selected bitline. A signal voltage is sensed on the selected bitline, the signal voltage being generated in response to the read current and the reference current. The signal voltage is coupled to an input of the sense amplifier, wherein the sense amplifier provides an offset corrected output reflective of the data state of the MRAM cell.

Abstract: A writeback and refresh circuit for a direct sense architecture memory wherein a plurality of primary sense amps are connected to a global data line and also to bitlines, each of which is coupled to an array of memory storage cells which are selected for write and read operations by a plurality of wordlines. A single secondary sense amp receives analog level data from the primary sense amps over the global data line, and includes a restore/writeback circuit which digitizes the data and then returns the digitized data over the global data line to the primary sense amp and back into the memory. A 2-cycle read/writeback operation is used for each memory read cycle, a first cycle read operation, and a second cycle writeback operation. The 2-cycle destructive read architecture eliminates the need for a cache and complex caching algorithms.

Abstract: In order to divert damaging currents into an electrostatic discharge (ESD) protection device during an ESD event, a tungsten wire resistor is incorporated into a current path connected in parallel with the ESD protection circuitry. The tungsten wire resistor has linear current-voltage (IV) characteristics at low currents, and non-linear IV characteristics at high current levels. The width and length of the resistor is chosen so that the resistor experiences significant self-heating caused by the higher currents generated by the ESD event. At a higher current level, the resistor becomes hot and its resistance increases dramatically. As a result the voltage drop across it increases thus diverting excess current into the parallel connected ESD protection circuitry. This limits the current through the resistor and thereby protects circuit elements in series with the resistor.

Abstract: A localized direct sense architecture circuit includes a large number (e.g. 8) of microcells, each having a primary sense amp PSA, coupled to one global data line which is coupled to one secondary sense amp SSA. Each PSA includes its own bias current device, which supplies bias current to sense devices in the PSA and is also used for precharge, such that the bias current does not flow along the highly capacitive global data line. With this technical approach, the size of each bias current supply device can be substantially reduced, and the number of PSAs on one global data line can be increased for increased layout density.

Abstract: A writeback and refresh circuit for a direct sense architecture memory wherein a plurality of primary sense amps are connected to a global data line and also to bitlines, each of which is coupled to an array of memory storage cells which are selected for write and read operations by a plurality of wordlines. A single secondary sense amp receives analog level data from the primary sense amps over the global data line, and includes a restore/writeback circuit which digitizes the data and then returns the digitized data over the global data line to the primary sense amp and back into the memory. A 2-cycle read/writeback operation is used for each memory read cycle, a first cycle read operation, and a second cycle writeback operation. The 2-cycle destructive read architecture eliminates the need for a cache and complex caching algorithms.

Abstract: A localized direct sense architecture circuit includes a large number (e.g. 8) of microcells, each having a primary sense amp PSA, coupled to one global data line which is coupled to one secondary sense amp SSA. Each PSA includes its own bias current device, which supplies bias current to sense devices in the PSA and is also used for precharge, such that the bias current does not flow along the highly capacitive global data line. With this technical approach, the size of each bias current supply device can be substantially reduced, and the number of PSAs on one global data line can be increased for increased layout density.

Abstract: A bipolar transistor is disclosed. The bipolar transistor comprises: a silicon substrate; a collector formed in the semiconductor substrate, a base formed over the collector, the base having an intrinsic base region and an extrinsic base region, the extrinsic base region forming an internal resistor, an emitter formed over the intrinsic base region; and a dielectric layer formed between the extrinsic base region and the collector, the extrinsic base region. the dielectric layer and the collector forming an internal capacitor. The base of the transistor may be silicon-germanium.

Abstract: A bipolar transistor is disclosed. The bipolar transistor comprises: a silicon substrate; a collector formed in the semiconductor substrate; a base formed over the collector, the base having an intrinsic base region and an extrinsic base region, the intrinsic base region forming an internal resistor; an emitter formed over the intrinsic base region; and a dielectric layer formed between the extrinsic base region and the collector, the extrinsic base region, the dielectric layer and the collector forming an internal capacitor. The base of the transistor may be silicon-germanium.

Abstract: The present invention relates generally to protection of integrated circuits from electrostatic discharges and more specifically to the use of devices formed in isolated well regions for electrostatic discharge protection. One aspect of the present invention is an ESD protection circuit that includes a first FET and a second FET. The drain of the first FET is coupled to an ESD susceptible node and the source of the first FET is coupled to a first voltage terminal. The gate and a well of the first FET are coupled together and to the drain of the second FET. The source of the second FET is coupled to the first voltage terminal. The gate of the second FET is coupled to a second voltage terminal. The second voltage terminal is connected to a voltage source that is at the first voltage when the circuit is not powered, and at a voltage above the threshold voltage of the second FET when the circuit is powered. The well in which the first FET is formed is electrically isolated from other wells in the substrate.

Abstract: A silicon-germanium ESD element comprises a substrate of a first dopant type coupled to a first voltage terminal and a first diode-configured element. The first diode-configured element has a collector region of a second dopant type in the substrate, a SiGe base layer of the first dopant type on the collector region, with the SiGe base layer including a base contact region, and an emitter of the second dopant type on the SiGe base layer. Preferably, the SiGe base layer ion the collector region is an epitaxial SiGe layer and the second dopant type of the emitter is diffused in to the SiGe base layer. The ESD element of the present invention may further include a second diode-configured element of the same structure as the first diode-configured element, with an isolation region in the substrate separating the first and second diode-configured elements. The first and second diode-configured elements form a diode network.