Abstract: A dynamic random access memory device (10) includes three separate sections--an input/output section (12), a peripheral transistor section (14), and a memory array section (16), all formed on a p- type substrate layer (18). The dynamic random access memory device (10) can employ separate substrate bias voltages for each section. The input/output section (12) has a p- type region (22) that is isolated from the p- type substrate layer (18) by an n- type well region (20). The peripheral transistor section (14) has a p- type region (36) that can be isolated from the p- type substrate layer (18) by an optional n- type well region (40) for those devices which require a different substrate bias voltage between the peripheral transistor section (14) and the memory array section (16).

Abstract: A DRAM array (100) having reduced bitline capacitance. The DRAM cell includes a pass transistor and a storage capacitor (150). An isolation structure (108) surrounds the DRAM cell. The bitline (140) is connected to a source/drain region (120b) of the pass transistor using a first polysilicon plug (112). A second polysilicon plug (110) connects the storage capacitor (150) to the other source/drain region (120a&c) of the pass transistor. Both polysilicon plugs (110, 112) extend through an interlevel dielectric layer (116) to one of the source/drain region (120a-c) of the pass transistor, but neither extends over the isolation structure (108). If desired, either the storage capacitor (150) or the bitline (140) may be offset from the source/drain regions (120a-c).

Abstract: A dynamic random access memory device (10) includes three separate sections--an input/output section (12), a peripheral transistor section (14), and a memory array section (16), all formed on a p- type substrate layer (18). The dynamic random access memory device (10) can employ separate substrate bias voltages for each section. The input/output section (12) has a p- type region (22) that is isolated from the p- type substrate layer (18) by an n-type well region (20). The peripheral transistor section (14) has a p- type region (36) that can be isolated from the p- type substrate layer (18) by an optional n- type well region (40) for those devices which require a different substrate bias voltage between the peripheral transistor section (14) and the memory array section (16).

Abstract: A method of improving the dielectric properties of a thin dielectric disposed on a polycrystalline material, a method of forming a capacitor therewith and the capacitor. An electrode (17) having a polycrystalline material surface having voids (23) extending to the surface, preferably silicon, is provided. A layer of an amorphous form of the material (19) having a thickness of from about 20 .ANG. to about 500 .ANG. is formed over the surface with the amorphous layer disposed within the voids. A thin layer of a dielectric (21) is formed over the amorphous layer and, in the fabrication of a capacitor, a layer of electrical conductor (25) is provided which is spaced from the material over the dielectric. A microcontaminant can be disposed between the polycrystalline material surface and the amorphous layer.

Abstract: The described embodiments of the present invention provide a memory cell and method for fabricating that memory cell and memory array including the cell. The memory cell is a trench capacitor type having a transistor (1-1-2) formed on the surface of a major face of a substrate (16) and having a capacitor (2-1-2) formed in the substrate around the periphery of a trench. The capacitor and transistor are connected by a buried, heavily doped region (26) having the opposite conductivity type from the substrate. A doped storage area (24) having the same doping type as the buried doped region surrounds the trench. A field plate (30) is formed in the trench separated from the storage region by a dielectric layer (32). The field plate extends onto the isolation areas between memory cells thus providing isolation between cells using a minimum of surface area.

Abstract: A method of reducing gated diode leakage in trench capacitor type field plate isolated dynamic random access memory devices is disclosed. Trenches are etched into a face of a body of semiconductor material. Storage nodes surrounding the trenches are created. A polysilicon layer is formed on the trench walls. A storage dielectric layer is formed on the trench walls, adjacent to the layer of polysilicon on the trench walls, so that the layer of polysilicon on the trench walls lies between the storage dielectric layer and the storage node. The layer of polysilicon on the trench walls reduces leakage current from the storage node. A trench type field plate isolated random access memory cell structure is also disclosed.

Abstract: A plurality of trenches (26, 28) of a DRAM cell array formed in a (P-) epitaxial layer (11) and a silicon substrate (12), and storage layers (38, 40) are grown on the sidewalls (34, 36) and bottom (not shown) of the trenches (26, 28). Highly doped polysilicon capacitor electrodes (42, 44) are formed in the trenches (26, 28). Sidewall oxide filaments (50, 54) and in situ doped sidewall conductive filaments (66, 68) are formed and thermal cycles are used to diffuse dopant from sidewall conductive filaments (66, 68) into upper sidewall portions (62, 64) to form diffused source regions (70, 72) of pass gate transistors (90) for each cell.

Abstract: A method of reducing gated diode leakage in trench capacitor type field plate isolated dynamic random access memory devices is disclosed. Trenches are etched into a face of a body of semiconductor material. Storage nodes surrounding the trenches are created. A polysilicon layer is formed on the trench walls. A storage dielectric layer is formed on the trench walls, adjacent to the layer of polysilicon on the trench walls, so that the layer of polysilicon on the trench walls lies between the storage dielectric layer and the storage node. The layer of polysilicon on the trench walls reduces leakage current from the storage node. A trench type field plate isolated random access memory cell structure is also disclosed.

Abstract: A memory cell comprises a semiconductor pillar and an insulator on a sidewall of the pillar. A conductive capacitor of the memory cell comprises a first electrode adjacent the insulator. A transistor of the memory cell is formed in the pillar and comprises a first source/drain region, a gate, and a second source/drain region coupled to the first electrode.

Abstract: A plurality of trenches (26, 28) of a DRAM cell array formed in a (P-) epitaxial layer (11) and a silicon substrate (12), and storage layers (38, 40) are grown on the sidewalls (34, 36) and bottom (not shown) of the trenches (26, 28). Highly doped polysilicon capacitor electrodes (42, 44) are formed in the trenches (26, 28). Sidewall oxide filaments (50, 54) and in situ doped sidewall conductive filaments (66, 68) are formed and thermal cycles are used to diffuse dopant from sidewall conductive filaments (66, 68) into upper sidewall portions (62, 64) to form diffused source regions (70, 72) of pass gate transistors (90) for each cell.

Abstract: Contact etching is simplified by including a conformal etch stop layer underneath the interlevel or multilevel oxide (MLO). Etching through the unequal thickness of the MLO with sufficient overetching to reliably clear the thickest parts of the MLO layer will therefore not damage the silicon contact areas underneath the thinner parts of the MLO. Process control is also improved.Preferably this conformal etch stop layer is a conductor, and is grounded to configure a field plate over the entire surface of the chip.

Abstract: The disclosure relates to the article and a method of forming a field oxide which extends over an isolation trench and the adjacent substrate wherein a portion of the trench insulating sidewall at the top region thereof is removed and replaced by polysilicon. The exposed silicon on the substrate and adjacent polysilicon are than oxidized to form the field oxide which is continuous, disposed above and contacts the remaining sidewall insulator in the trench.

Abstract: The described embodiments of the present invention provide a memory cell and method for fabricating that memory cell and memory array including the cell. The memory cell is a trench capacitor type having a transistor (1-1-2) formed on the surface of a major face of a substrate (16) and having a capacitor (2-1-2) formed in the substrate around the periphery of a trench. The capacitor and transistor are connected by a buried, heavily doped region (26) having the opposite conductivity type from the substrate. A doped storage area (24) having the same doping type as the buried doped region surrounds the trench. A field plate (30) is formed in the trench separated from the storage region by a dielectric layer (32). The field plate extends onto the isolation areas between memory cells thus providing isolation between cells using a minimum of surface area.

Abstract: A latch-up free CMOS structure and method of fabrication thereof is disclosed. A P-type substrate (40) is appropriately masked to form a plurality of sites in which isolated wells (50) are formed. A thermal oxide layer (56) is grown on the surface of each well (50), and a boron channel stop (62) implanted therearound. Polysilicon semiconductor material (68) is formed within each well, and implant doped to form an N-well (76) of material. The P-substrate (40) is planarized. PMOS transistors are formed within the oxide isolate N-wells (76), while NMOS transistors are formed in the P-substrate (40) outside the wells.

Abstract: A MOS bulk device having source/drain-contact regions 36 which are almost completely isolated by a dielectric 35. These "source/drain" regions 36 formed by using a silicon etch to form a recess, limiting the etched recess with oxide, and backfilling with polysilicon. A short isotropic oxide etch, followed by a polysilicon filament deposition, then makes contact between the oxide-isolated source/drain-contact regions 36 and the channel region 33 of the active device. Outdiffusion through the small area of this contact will form small diffusioins 44 in silicon, which act as the electrically effective source/drain regions. Use of sidewall nitride filaments 30 on the gate permits the silicon etch step to be self-aligned.

Abstract: A trench capacitor (10) has a center portion (26) formed from the substrate (14) by a tubular trench (24). A conducting layer (32) is deposed within the tubular trench (24) and is separated from the substrate (14) and center portion (26) by a dielectric layer (30). Since the charge storage area and the trench capacitor (10) includes both the inside and outside of the trench (24), a greater surface area is obtained, thereby increasing the capacitance of the device. A memory cell (34) may be implemented using the capacitor (10).

Abstract: Preferred embodiments include channel stop implants for CMOS devices by through field boron implants (152) after the field oxide (144, 145) has been grown and with the implant depth determined by the thin portions of the field oxide (145). Junction (154) breakdown is preserved by channeling the implant (152) to penetrate far below the junctions (154).

Abstract: The specification discloses an isolation trench (36) formed in a semiconductor body. A stress relief layer (38) of oxide is formed on the interior walls of the trench (36), the layer (38) being sufficiently thin to prevent stressing of the lower corners of the trench (36). A masking layer (40) of nitride is formed over the layer (38). An isolation body (42) of oxide or polysilicon then refills the remainder of the trench and a cap oxide (43) and layer (44) of field oxide is formed over the semiconductor body and the filled trench.

Abstract: A MOS bulk device having source/drain-contact regions 36 which are almost completely isolated by a dielectric 35. These "source/drain" regions 36 are formed by using a silicon etch to form a recess, lining the etched recess with oxide, and backfilling with polysilicon. A short isotropic oxide etch, followed by a polysilicon filament deposition, then makes contact between the oxide-isolated source/drain-contact regions 36 and the channel region 33 of the active device. Outdiffusion through the small area of this contact will form small diffusions 44 in silicon, which act as the electrically effective source/drain regions. Use of sidewall nitride filaments 30 on the gate permits the silicon etch step to be self-aligned.

Abstract: A trench (28) of a DRAM cell is formed in a (p-) epitaxial layer (10) and a silicon substrate (12), and a storage oxide (32) is grown on the sidewalls (30) of the trench (28). A highly doped polysilicon capacitor electrode (34) is formed in the trench (28). A portion (52) of the storage oxide (32) is removed from a selected side of the sidewalls (30), and a plug (68) is deposited therein and etched back so that the electrode (34) is connected to the epitaxial layer (10). A thermal cycle is used to diffuse dopant from the capacitor electrode (34) into and through the plug (68) and into the adjacent semiconductor layer (10) to make the plug (68) conductive and to form a source region (66) of a pass gate transistor of the cell.