Abstract: An improved memory cell layout (54) is formed including a trench cell (60) formed in a semiconductor substrate (58). The memory cell layout (54) includes a bitline (56) and a wordline (62) for storing and accessing charge. The charge is stored on a capacitor formed from a conductor (68), an insulating region (70) and a semiconductor substrate (58). Bitline (56) is primarily tangential to a trench cell (60), or may surround the periphery thereof. A wordline (62) overlies trench cell (60) and extends therein, and further may be formed of a width narrower than trench cell (60).

Abstract: A latch-up free CMOS structure and method of fabrication thereof is disclosed. A P-type substrate (40) is appropriately masked to form a plurality of sites in which isolated wells (50) are formed. A thermal oxide layer (56) is grown on the surface of each well (50), and a boron channel stop (62) implanted therearound. Polysilicon semiconductor material (68) is formed within each well, and implant doped to form an N-well (76) of material. The P-substrate (40) is planarized. PMOS transistors are formed within the oxide isolated N-wells (76), while NMOS transistors are formed in the P-substrate (40) outside the wells.

Abstract: The described embodiments of the present invention provide structures, and a method for fabricating those structures, which include a memory cell formed within a single trench. A trench is formed in the surface of a semiconductor substrate. The bottom portion of the trench is filled with polycrystalline silicon to form one plate of a storage capacitor. The substrate serves as the other plate of the capacitor. The remaining portion of the trench is then filled with an insulating material such as silicon dioxide. A pattern is then etched into the silicon dioxide when opens a portion of the sidewall and the top portion of the trench down to the polycrystalline capacitor plate. A contact is then formed between the polycrystalline capacitor plate and the substrate. Dopant atoms diffuse through the contact to form a source region on a sidewall of the trench. A gate insulator is formed by oxidation and a drain is formed at the surface of the trench adjacent to the mouth of the trench.

Abstract: A multiple recess isolation technology avoids stress induced defects while providing a substantially planar surface. A silicon substrate (10) is patterned and etched, creating active moat regions (18) and recesses (20a-b and 21a-b). the recesses are filled with oxide by growing a field oxide (40) in wide recessed regions (21) using a LOCOS process, while depositing a planarization field oxide (44) in narrow recessed regions (20). After etching the structure to obtain a planar surface, standard procedures are used to fabricate the active devices. The process uses a single photolithographic masking step and results in only a very small loss of the width electrically active regions.

Abstract: Preferred embodiments include channel stop implants for CMOS devices by through field boron implants (152) after the field oxide (144, 145) has been grown and with the implant depth determined by the thin portions of the field oxide (145). Junction (154) breakdown is preserved by channeling the implant (152) to penetrate far below the junctions (154).

Abstract: The following detailed description describes a dynamic random access memory (dRAM) cell. The described cell provides a one-transistor/one-capacitor dRAM cell structure and array in which the cell pass transistor is formed on the sidewalls of a trench containing the cell capacitor; the word and bit lines cross over this trench. The trench extends through an epitaxial layer into a substrate. The epitaxial layer and substrate are separated by a layer which serves as a diffusion barrier. This stacking of the transistor on top of the capcitor yields a cell with minimal area on the substrate and solves a problem of dense packing of cells. The diffusion barrier allows for the optimal doping of the epitaxial for operation of the transistor and optimal doping of the substrate for operation of the capacitor.

Abstract: A multiple recess isolation technology avoids stress induced defects while providing a substantially planar surface. A silicon substrate (10) is patterned and etched, creating active moat regions (18) and recesses (20a-b and 21a-b). The recesses are filled with oxide by growing a field oxide (40) in wide recessed regions (21) using a LOCOS process, while depositing a planarization field oxide (44) in narrow recessed regions (20). After etching the structure to obtain a planar surface, standard procedures are used to fabricate the active devices. The process uses a single photolithographic masking step and results in only a very small loss of the width electrically active regions.

Abstract: The described embodiments of the present invention provide structures, and a method for fabricating those structures, which include a memory cell formed within a single trench. A trench is formed in the surface of a semiconductor substrate. The bottom portion of the trench is filled with polycrystalline silicon to form one plate of a storage capacitor. The substrate serves as the other plate of the capacitor. The remaining portion of the trench is then filled with an insulating material such as silicon dioxide. A pattern is then etched into the silicon dioxide which opens a portion of the sidewall and the top portion of the trench down to the polycrystalline capacitor plate. A contact is then formed between the polycrystalline capacitor plate and the substrate. Dopant atoms diffuse through the contact to form a source region on a sidewall of the trench. A gate insulator is formed by oxidation and a drain is formed at the surface of the trench adjacent to the mouth of the trench.

Abstract: Using a structure according to one embodiment of the present invention, active elements in integrated circuitry may be completely isolated from other elements in the integrated circuitry by silicon dioxide regions surrounding the sides of the region containing the active element and a buried diffusion beneath the active element extending to all sides of the isolating silicon dioxide regions.In one embodiment of the present invention, an isolation structure is fabricated by etching a silicon substrate to remove the silicon from the entire region occupied by the isolated active area and the isolation structure of this embodiment of the invention. A conformal layer of silicon dioxide, or other dielectric material, is then deposited on the surface of the silicon substrate. The conformal silicon dioxide layer is then anisotropically etched to remove the silicon dioxide on the bottom of the isolation region but still provide a sidewall region of silicon dioxide on the sides of the isolation region.

Abstract: Integrated circuits wherein the width of contacts is narrowed by a sidewall oxide, so that the metal layer can be patterned to minimum geometry everywhere, and does not have to be widened where it runs over a contact.

Abstract: The specification discloses an isolation trench (36) formed in a semiconductor body. A stress relief layer (38) of oxide is formed on the interior walls of the trench (36), the layer (38) being sufficiently thin to prevent stressing of the lower corners of the trench (36). A masking layer (40) of nitride is formed over the layer (38). An isolation body (42) of oxide or polysilicon then refills the remainder of the trench and a cap oxide (43) and layer (44) of field oxide is formed over the semiconductor body and the filled trench.

Abstract: An integrated circuit isolation technology wherein the nitride-sidewall methods of the prior art are improved by performing an undercut and backfill before the second nitride (the sidewall nitride which prevents encroachment) is added to the first nitride (which covers the moat areas). Thus, the butt joint between the two nitrides is made more secure, and localized bird's-beaking at the butt joint between the moat nitride and the sidewall nitride does not occur.

Abstract: A sidewall-nitride isolation technology refines process control over lateral oxide encroachment by preventing any thinning of the nitride moat-masking layer during the nitride etch step which clears the sidewall nitride layer from the bottom of the etched recesses in silicon. This is done by initially patterning the moat regions in an oxide/nitride/oxide stack, rather than the nitride/oxide stack of the prior art.