Patents by Inventor Claude Marie

Claude Marie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150238480
    Abstract: The present invention relates to compounds of the formula (I), salts thereof, to pharmaceutical compositions containing them and their use in medicine. In particular, the invention relates to compounds as activators of AMPK.
    Type: Application
    Filed: May 11, 2015
    Publication date: August 27, 2015
    Inventors: Alain Claude-Marie DAUGAN, Yann LAMOTTE, Olivier MIRGUET
  • Patent number: 9075621
    Abstract: A data processing apparatus executes instructions in a sequence of pipelined execution stages. An error detection unit twice samples a signal associated with execution of an instruction and generates an error signal if the samples differ. An exception storage unit maintains an age-ordered list of entries corresponding to instructions issued to the execution pipeline and can mark an entry to show if the error signal has been generated in association with that instruction. A timer unit is responsive to generation of the error signal to initiate timing of a predetermined time period. An error recovery unit initiates a soft pipeline flush procedure if an oldest pending entry in the list has said error marker stored in association therewith and initiates a hard pipeline flush procedure if said predetermined time period elapses, said hard flush procedure comprising resetting said pipeline to a predetermined state.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: July 7, 2015
    Assignee: ARM Limited
    Inventors: Guillaume Schon, Mélanie Emanuelle Lucie Teyssier, Frederic Claude Marie Piry, Luca Scalabrino, David Michael Bull
  • Patent number: 9061998
    Abstract: The present invention relates to compounds of the formula (I), salts thereof, to pharmaceutical compositions containing them and their use in medicine. In particular, the invention relates to compounds as activators of AMPK.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: June 23, 2015
    Assignee: GlaxoSmithKline LLC
    Inventors: Alain Claude-Marie Daugan, Olivier Mirguet, Yann Lamotte
  • Patent number: 9052909
    Abstract: A data processing apparatus with a processing pipeline, the pipeline including exception control circuitry and error detection circuitry. An exception storage unit is configured to maintain an age-ordered list of entries corresponding to instructions issued to the processing pipeline for execution. The unit is configured to store, in association with each entry, an exception indicator indicating whether the instruction is an exception instruction and whether it has generated an exception and an error indicator indicating whether the instruction has generated an error. The apparatus is configured to indicate to the exception storage unit that an instruction is resolved when processing of the instruction has reached a stage such that it is known whether the instruction will generate an error and whether the instruction will generate an exception; and the exception control circuitry is configured to sequentially retire oldest resolved entries from the list in the exception storage unit.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: June 9, 2015
    Assignee: ARM Limited
    Inventors: Frederic Claude Marie Piry, Luca Scalabrino, Guillaume Schon, Melanie Emanuelle Lucie Teyssier
  • Publication number: 20150140629
    Abstract: The invention relates to an alcoholic fermentation process in the presence of one or more high alcohol tolerant yeast and one or more maltotriose positive yeast. The process of the present invention can be a fermentation process for the production of ethanol, for the production of beer, for the production of wine and the like, in a preferred embodiment, the present invention relates to a process for the production of ethanol in the presence of distiller's yeast and baker's yeast.
    Type: Application
    Filed: May 31, 2013
    Publication date: May 21, 2015
    Applicant: Cargill, Incorporated
    Inventors: Jean-Claude Marie Pierre De Troostembergh, Bernhard Horbach, Michael Josef Christian Kruse, Nicolas Andre Albert Meurens
  • Publication number: 20150104868
    Abstract: The present invention relates to methods of using meso-1,2,3,4-tetrahydroxybutane for the maintenance and/or improvement of biological cell function and activity, and for the prevention of improper cell functioning or cell death, in vitro, ex vivo, and in vivo over time and/or during exposure to stress. Meso-1,2,3,4-tetrahydroxybutane can be used to promote cell survival and as a cell protection agent, to increase cell viability, and to improve conversion of progenitor or stem cells to mature cells, whether in vitro, in vivo, ex-vivo, or transplanted.
    Type: Application
    Filed: April 19, 2013
    Publication date: April 16, 2015
    Applicant: CARGILL, INC.
    Inventors: Alvin Berger, Aalt Bast, Petrus Wilhelmus Hubertus De Cock, Gerardus Johannes Martinus Den Hartog, Jean-Claude Marie-Pierre Ghislain De Troostembergh
  • Publication number: 20140310480
    Abstract: A data processing apparatus is provided in which a processor unit accesses data values stored in a memory and a cache stores local copies of a subset of the data values. The cache maintains a status value for each local copy stored in the cache. When the processor unit executes a load-exclusive operation, a first data value is loaded from a specified memory location and an exclusive use monitor begins monitoring the specified memory location for accesses. When the processor unit executes a store-exclusive operation, a second data value is stored to the specified memory location if the exclusive use monitor indicates that the first data value has not been modified since the load-exclusive operation was executed.
    Type: Application
    Filed: April 12, 2013
    Publication date: October 16, 2014
    Inventors: Frederic Claude Marie PIRY, Philippe Jean-Pierre RAPHALEN, Melanie Emanuelle Lucie TEYSSIER, Albin Pierick TONNERRE
  • Publication number: 20140215189
    Abstract: An apparatus and method includes execution circuitry including a wide operand execution unit configured to allow up to N bits of operand data to be processed during execution of a single instruction. Decoder circuitry decodes and generates, for each instruction, at least one control data block identifying an operation to be performed by the execution circuitry and at least two re-combineable control data blocks for the instruction. Issue queue control circuitry then allocates a slot in the issue queue for each of the at least two data blocks and up to M bits of associated operand data, and marks those allocated slots to identify that they contain re-combineable control data blocks. The issue queue control circuitry issues the combined block to said wide operand execution unit along with the operand data contained in each of the allocated slots for said at least two control data blocks.
    Type: Application
    Filed: January 29, 2013
    Publication date: July 31, 2014
    Applicant: ARM LIMITED
    Inventors: Cedric Denis Robert AIRAUD, Luca SCALABRINO, Frederic Jean Denis ARSANTO, Guillaume SCHON, Frederic Claude Marie PIRY, Albin Pierick TONNERRE
  • Publication number: 20140164742
    Abstract: An apparatus and method are provided for performing register renaming. Available register identifying circuitry is provided to identify which physical registers form a pool of physical registers available to be mapped by register renaming circuitry to an architectural register specified by an instruction to be executed. Configuration data whose value is modified during operation of the processing circuitry is stored such that, when the configuration data has a first value, the configuration data identifies at least one architectural register of the architectural register set which does not require mapping to a physical register by the register renaming circuitry. The register identifying circuitry is arranged to reference the modified data value, such that when the configuration data has the first value, the number of physical registers in the pool is increased due to the reduction in the number of architectural registers which require mapping to physical registers.
    Type: Application
    Filed: June 26, 2013
    Publication date: June 12, 2014
    Inventors: Frederic Claude Marie PIRY, Louis-Marie Vincent MOUTON, Luca SCALABRINO, Richard Roy GRISENTHWAITE, David Hennah MANSELL
  • Patent number: 8738971
    Abstract: A data processing apparatus configured to operate in a voltage and frequency operating region that is located beyond a safe region where errors do not arise, but within operating region limits such that the errors are rare. The data processing apparatus comprises: error detection circuitry and error recovery circuitry; the error detection circuitry being configured to determine if a signal sampled in the processing apparatus changes within a time window occurring after the signal has been sampled and during a same clock cycle as the sampling and to signal an error if the signal does change.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: May 27, 2014
    Assignee: ARM Limited
    Inventors: Frederic Claude Marie Piry, Luca Scalabrino, David Michael Bull
  • Patent number: 8640008
    Abstract: A data processing apparatus has error detection units each configured to generate an error signal if a first and second sample of a signal associated with execution of an instruction differ. Error value generation circuitry generates an error value showing if any of the error detection units have generated the error signal. Error value stabilisation circuitry performs a stabilisation procedure comprising re-sampling the error value to remove metastability. Error recovery circuitry initiates re-execution of the instruction if the error value is asserted. Count circuitry holds a counter value in association with the error value, the counter value set to a predetermined value when the error value is generated and decremented each time the error value is re-sampled prior to reaching the error value stabilisation circuitry. The error value bypasses the stabilisation procedure if the counter value is zero before the error value reaches the error value stabilisation circuitry.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: January 28, 2014
    Assignee: ARM Limited
    Inventors: Guillaume Schon, Luca Scalabrino, Frederic Claude Marie Piry, David Michael Bull
  • Publication number: 20130345243
    Abstract: The present invention relates to pyrimidinedione compounds of formula (I), salts thereof, to pharmaceutical compositions containing them and their use in medicine. In particular, the invention relates to compounds of formula (I) or salts thereof as activators of AMPK.
    Type: Application
    Filed: March 5, 2012
    Publication date: December 26, 2013
    Applicant: GLAXOSMITHKLINE LLC
    Inventors: Anne Marie Jeanne Bouillot, Alain Claude-Marie Daugan, Yann Lamotte, Olivier Mirguet
  • Publication number: 20130345212
    Abstract: The present invention relates to compounds of the formula (I), salts thereof, to pharmaceutical compositions containing them and their use in medicine. In particular, the invention relates to compounds as activators of AMPK.
    Type: Application
    Filed: March 5, 2012
    Publication date: December 26, 2013
    Applicant: GLAXOSMITHKLINE LLC
    Inventors: Alain Claude-Marie Daugan, Olivier Mirguet, Yann Lamotte
  • Patent number: 8578136
    Abstract: An apparatus and method are provided for performing register renaming, whereby architectural registers from a set of architectural registers are mapped to physical registers from a set of physical registers. Available register identifying circuitry is provided which is responsive to a current state of the apparatus to identify which physical registers form a pool of physical registers available to be mapped by register renaming circuitry to an architectural register specified by an instruction to be executed. Configuration storage stores configuration data whose value is modified during operation of the processing circuitry, such that when the configuration data has a first value, the configuration data identifies at least one architectural register of the architectural register set which does not require mapping to a physical register by the register renaming circuitry.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: November 5, 2013
    Assignee: ARM Limited
    Inventors: Frederic Claude Marie Piry, Louis-Marie Vincent Mouton, Luca Scalabrino, Richard Roy Grisenthwaite, David Hennah Mansell
  • Publication number: 20130166980
    Abstract: A data processing apparatus has error detection units each configured to generate an error signal if a first and second sample of a signal associated with execution of an instruction differ. Error value generation circuitry generates an error value showing if any of the error detection units have generated the error signal. Error value stabilisation circuitry performs a stabilisation procedure comprising re-sampling the error value to remove metastability. Error recovery circuitry initiates re-execution of the instruction if the error value is asserted. Count circuitry holds a counter value in association with the error value, the counter value set to a predetermined value when the error value is generated and decremented each time the error value is re-sampled prior to reaching the error value stabilisation circuitry. The error value bypasses the stabilisation procedure if the counter value is zero before the error value reaches the error value stabilisation circuitry.
    Type: Application
    Filed: December 23, 2011
    Publication date: June 27, 2013
    Inventors: Guillaume SCHON, Luca Scalabrino, Frederic Claude Marie Piry, David Michael Bull
  • Publication number: 20130166952
    Abstract: A data processing apparatus executes instructions in a sequence of pipelined execution stages. An error detection unit twice samples a signal associated with execution of an instruction and generates an error signal if the samples differ. An exception storage unit maintains an age-ordered list of entries corresponding to instructions issued to the execution pipeline and can mark an entry to show if the error signal has been generated in association with that instruction. A timer unit is responsive to generation of the error signal to initiate timing of a predetermined time period. An error recovery unit initiates a soft pipeline flush procedure if an oldest pending entry in the list has said error marker stored in association therewith and initiates a hard pipeline flush procedure if said predetermined time period elapses, said hard flush procedure comprising resetting said pipeline to a predetermined state.
    Type: Application
    Filed: December 23, 2011
    Publication date: June 27, 2013
    Applicant: ARM Limited
    Inventors: Guillaume Schon, Mélanie Emanuelle Lucie Teyssier, Frederic Claude Marie Piry, Luca Scalabrino, David Michael Bull
  • Publication number: 20130151891
    Abstract: A data processing apparatus configured to operate in a voltage and frequency operating region that is located beyond a safe region where errors do not arise, but within operating region limits such that the errors are rare. The data processing apparatus comprises: error detection circuitry and error recovery circuitry; the error detection circuitry being configured to determine if a signal sampled in the processing apparatus changes within a time window occurring after the signal has been sampled and during a same clock cycle as the sampling and to signal an error if the signal does change.
    Type: Application
    Filed: December 7, 2011
    Publication date: June 13, 2013
    Applicant: ARM LIMITED
    Inventors: Frederic Claude Marie Piry, Luca Scalabrino, David Michael Bull
  • Publication number: 20130151819
    Abstract: A data processing apparatus with a processing pipeline, the pipeline including exception control circuitry and error detection circuitry. An exception storage unit is configured to maintain an age-ordered list of entries corresponding to instructions issued to the processing pipeline for execution. The unit is configured to store, in association with each entry, an exception indicator indicating whether the instruction is an exception instruction and whether it has generated an exception and an error indicator indicating whether the instruction has generated an error. The apparatus is configured to indicate to the exception storage unit that an instruction is resolved when processing of the instruction has reached a stage such that it is known whether the instruction will generate an error and whether the instruction will generate an exception; and the exception control circuitry is configured to sequentially retire oldest resolved entries from the list in the exception storage unit.
    Type: Application
    Filed: December 7, 2011
    Publication date: June 13, 2013
    Applicant: ARM LIMITED
    Inventors: Frederic Claude Marie PIRY, Luca SCALABRINO, Guillaume SCHON, Melanie Emanuelle Lucie TEYSSIER
  • Publication number: 20120282299
    Abstract: The present invention relates to a coating comprising at least one biodegradable polymer, wherein the polymer comprises at least one or a blend of a poly (ester amide) (PEA) having a chemical formula described by structural formula (II), wherein; R1 is independently selected from the group consisting of (C2-C20)alkylene, (C2-C20)alkenylene, —(R9—CO—O—R10—O—CO—R9)—, CHR11—O—CO—R12—COOCR11— and combinations thereof; R3 and R4 in a single co-monomer m or p, respectively, are independently selected from the group consisting of hydrogen, (C1-C6)alkyl, (C2-C6)alkenyl, (C2-C6)alkynyl, (C6-C10)aryl, (C1C6)alkyl, —(CH2)SH, —(CH2)2S(CH3), CH2OH, —CH(OH)CH3, —(CH2)4NH3+, ˜(CH2)3NHC(?NH2+)NH2, —CH2COOH, (CH2)COOH, —CH2—CO—NH2—CH2CH2—CO—NH2, —CH2CH2COOH, CH3—CH2—CH(CH3)—, formula (a), HO—P-Ph-CH2—, (CH3)2—CH—, Ph-NH—, NH—(CH2)3—C—, NH—CH?N—CH?C—CH2—.
    Type: Application
    Filed: October 18, 2010
    Publication date: November 8, 2012
    Inventors: Soazig Claude Marie Delamarre, George Mihov, Astrid Franken, Kenneth Alan Messier
  • Patent number: 8271730
    Abstract: A plurality of processing units for performing data processing operations require access to data in shared memory. Each has an associated cache storing a subset of the data for access by that processing unit. A cache coherency protocol ensures data accessed by each unit is up-to-date. Each unit issues a write access request when outputting a data value for storing in shared memory. When the write access request requires both the associated cache and the shared memory to be updated, a coherency operation is initiated within the cache coherency logic. The coherency operation is performed for all of the caches including the cache associated with the processing unit that issued the write access request in order to ensure that the data in those caches is kept coherent.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: September 18, 2012
    Assignee: ARM Limited
    Inventors: Frederic Claude Marie Piry, Philippe Jean-Pierre Raphalen, Norbert Bernard Eugéne Lataille, Stuart David Biles, Richard Roy Grisenthwaite