Abstract: In a power converter circuit directly or indirectly connected to the power distribution network, the protection from voltage spikes which may occur on the power supply rail is implemented in a manner as to consent the utilization of at least a portion of the energy associated with the spike by storing portion of said energy in the reactive components of the converter circuit itself instead of dissipating completely the energy through a dissipating elements as in prior art arrangements. The novel circuit arrangement utilizes one or two spike sensors the output signal or signals of which are fed to logic gates which determine a certain configuration of the analog switches of the converter circuit. A protection voltage limiting element (zener diode, avalanche diode, voltage-dependent resistor, etc.

Abstract: In this MOS-transistor bridge circuit, for obtaining a fast flyback conduction of the current after a normal operation of the circuit, instead of the flyback diodes associated with each transistor of the bridge, the MOS transistors themselves are employed, driven so as to conduct current from the ground to the power supply, that is in the opposite direction with respect to that of normal operation. For this purpose a control section is provided receiving at the input a fast flyback signal and comprising delay gates connected to the disable inputs of the transistors, so as to delay switching off thereof, and to maintain in the on state two diagonally opposed transistors so as to allow current to flow from the ground to the power supply through these diagonally opposed transistors and the load until the current decreases to zero.

Abstract: A CMOS logic circuit for sampling data coming from TTL logic circuits under frequency control by a system's clock intrinsically faster than prior art similar circuits is obtained by combining a TTL/CMOS compatibility interface inverting stage with a first stage of the sampling circuit (master or latch stage). The circuit of the invention permits elimination of two inverters and therefore reduction of data transfer delay.

Abstract: This charge pump circuit comprises a capacitor connected with a first terminal thereof to a reference voltage point through a first switch element and with a second terminal thereof to a switching section. The switching section, which is arranged between a positive supply voltage line and the ground, is controlled so as to alternately and selectively connect the second terminal of the capacitor to the positive supply and to ground. The first terminal of the capacitor is further connected to the gate of the MOS transistor to be driven. During operation the switch section is controlled so as to alternately charge the capacitor and allow transfer of the charge of the capacitor to the MOS transistor gate, thereby achieving a fast charging of the MOS transistor and a low circuit dissipation in the DC mode.

Abstract: This circuit, for reliably driving a load both in DC and AC mode with a low dissipation, comprises a pair of MOS power transistors, in a push-pull configuration, and a bootstrap circuit including a bootstrap capacitor placed between the source of the upper MOS transistor and a reference voltage point, through a first switch. A second switch is arranged between the supply line and the gate of the upper MOS transistor, while a third switch is arranged between the gate of the upper MOS transistor and the point common to the first switch and the bootstrap capacitor. During DC operation, the switches are open or closed in order to allow for the connection of the gate of the MOS power transistor to the supply voltage. During AC operation, the switches are controlled thereby, alternately the capacitor is charged at the voltage of the reference voltage point and the upper MOS transistor is held at a gate-to-source voltage sufficient to feed the load.

Abstract: The switching driving device with current limitation, operating reliably even with high switching frequencies, comprises a drive stage receiving at the input a timing clock signal at a preset frequency and generating at the output a drive signal synchronized with the timing clock signal, a power element connected at the input to the drive stage, receiving therefrom the drive signal and generating a load supply signal, a load fed by the power element, and a current sensor generating an overload signal when the current in the load has reached a preset threshold. The current limitation is obtained through a memory element connected to the current sensor and disabling the drive stage in the presence of the overload signal. In order to obtain a reliable operation, in the presence of the overload signal the drive stage is controlled at a switching frequency which is lower than the preset frequency of the timing clock signal.

Abstract: A monolithically integrable high-efficiency control circuit for the switching of transistors includes a first transistor whose base terminal is connected to a source of switching signals. A second transistor whose base is connected to a current generator, drives a third transistor which connected in series with the first transistor such that the first and third transistors are connected between two terminals of a supply voltage generator. The emitter terminal of the third transistor forms an output terminal of the control circuit and is connected to the collector terminal of the first transistor by means of a parallel connected diode and a resistor combination. The circuit also includes a fourth transistor, whose base terminal is connected through a resistor to the base terminal of the third transistor and whose collector and emitter terminals are respectively connected to the base terminal of the second transistor and to the collector terminal of the first transistor.

Abstract: In an audio switching power amplifier, muting apparatus provided for eliminating noise signals associated with turn-on and turn-off operations of the apparatus is disclosed. The muting apparatus disables the output power amplifiers and controls signal levels at various positions in the power amplifier to reduce transient conditions. Control apparatus applies the muting signals to the power amplifier during a predetermined period during start-up of the amplifier and applies the muting conditions immediately upon the turning off of power to the power amplifier.

Abstract: This operational amplifier has an output range comprised between values adjustable as desired and includes a differential input stage and an output gain stage, and two additional differential stages supplied at one input with the output voltage of the operational amplifier and at the other input each with a reference voltage representing either the upper limit or the lower limit of the sought range. The outputs of the two additional differential stages are connected to the input stage of the operational amplifier such as not to interfere with the latter when the output voltage of the operational amplifier is comprised between the range limits and to allow switching off and functional substitution of the input stage for either differential stage when the operational amplifier output is equal to the reference voltage of this differential stage, so as to hold that reference voltage at the operational amplifier output regardless of the signal at the input to the operational amplifier.

Abstract: A bistable multivibrator circuit includes two main transistors and two other transistors and an additional pair of transistors. The multivibrator circuit can be monolithically integrated and has an output that can be placed in a preferential state. The two other transistors are utilized to set and reset the multivibrator circuit while the two additional transistors form a control circuit for controlling the multivibrator circuit so as to cause its outputs to be in a prescribed preferential state.

Abstract: A control circuit for switching inductive loads which can be monolithically integrated and used in high-speed printing equipment and in chopper power supply systems. The circuit includes a final power transistor, driven for switching by means of a drive transistor coupled to its control terminal. A speedup circuit is connected to the control terminals of both of the transistors in order to accelerate the turning off of the transistors by reducing the discharge time thereof. Such a speedup circuit is enabled so as to remove charge carriers only for a period of time which begins when the transistors are turned off in order to avoid additional time delays when the transistors are subsequently turned on again.