Abstract: Various aspects of the disclosure are directed to methods and apparatuses involving communications. As consistent with one or more embodiments, first and second sets of multiple current drivers are implemented respectively in a high-side and a low-side circuit. Current is driven via an output port in the high-side circuit by activating the first set of multiple current drivers until a steady-state high voltage is detected, and by deactivating one of the current drivers in the first set when the steady-state high voltage is detected. Current is driven in the low-side circuit by activating the second set of multiple current drivers until a steady-state low voltage is detected, and by deactivating one of the current drivers in the second set when the steady-state low voltage is detected.

Abstract: Various exemplary aspects are directed to apparatuses and methods involving switches communicatively-coupled on a bus where one or more of the switches operate to block signals from passing through the switch in a first mode, and to pass signals through the switch in a second mode. A logic circuit is responsive to addressing information received in the first mode, by storing and configuring the apparatus with the address information. The logic circuit ignores address information received in the second mode (e.g., does not reconfigure the apparatus with address information received in the second mode).

Abstract: A power supply circuit and a method for operating a power supply circuit involves selecting a normal operational mode or a pass-through operational mode for a switched mode power supply, in the normal operational mode, converting an input voltage of a power supply circuit to an intermediate voltage using a switching regulator of the switched mode power supply, in the pass-through operational mode, disabling the switching regulator such that the input voltage of the power supply circuit is unchanged by the switching regulator and an electric current consumption of the switching regulator approaches zero, and converting the intermediate voltage or the input voltage of the power supply circuit to an output voltage using a linear voltage regulator.

Abstract: A power supply regulator circuit uses a feedback loop to control current through a first output transistor from a power supply input to a regulated power supply output. The first output transistor is included in an integrated circuit. In order to avoid heating of the integrated circuit in excess of an acceptable level due to permanent supply of a high current through the first transistor, current through a second output transistor in parallel with the first transistor, but outside the integrated circuit is raised when it is detected that the current through the first output transistor exceeds a threshold level. The second output transistor outside the integrated circuit serves to take over supply of a part of the power supply current from first output transistor inside integrated circuit, when long term supply of that part from first output transistor would lead to undesirable heating of the integrated circuit. During a limited time interval a first transistor current above the threshold level is acceptable.

Abstract: Various exemplary embodiments relate a system for supplying power. The system may include a power source outputting a source voltage, a regulator connected to the power source, and an extension module connected to the power source. The regulator may output a first voltage when the source voltage is above a minimum threshold, and the extension module may output a second voltage when the source voltage falls below the minimum threshold.

Abstract: Various exemplary embodiments relate a system and method for supplying power. The system may include an input/output port, a regulator, and a clamp. The regulator may supply power to the input/output port in a first mode, sink current from the input/output port in a second mode, and be disabled in a third mode. The clamp may be disabled in the first and second modes, and may limit the voltage at the input/output port below a first value in the third mode.

Abstract: Various exemplary aspects are directed to apparatuses and methods involving switches communicatively-coupled on a bus where one or more of the switches operate to block signals from passing through the switch in a first mode, and to pass signals through the switch in a second mode. A logic circuit is responsive to addressing information received in the first mode, by storing and configuring the apparatus with the address information. The logic circuit ignores address information received in the second mode (e.g., does not reconfigure the apparatus with address information received in the second mode).

Abstract: An output driver circuit is provided. In accordance with various example embodiments, an output driver circuit includes a high-side driver circuit having transistors coupled in anti-series between a power source and an output node, and a low-side driver circuit having transistors coupled in anti-series between the output node and ground. For each transistor, a diode is connected between the source and drain of the transistor, with the diodes of the respective high-side and low-side circuits being arranged to prevent/mitigate the flow of current in opposite directions.

Abstract: An output driver circuit is provided. In accordance with various example embodiments, an output driver circuit includes a high-side driver circuit having transistors coupled in anti-series between a power source and an output node, and a low-side driver circuit having transistors coupled in anti-series between the output node and ground. For each transistor, a diode is connected between the source and drain of the transistor, with the diodes of the respective high-side and low-side circuits being arranged to prevent/mitigate the flow of current in opposite directions.

Abstract: A power supply circuit and a method for operating a power supply circuit involves selecting a normal operational mode or a pass-through operational mode for a switched mode power supply, in the normal operational mode, converting an input voltage of a power supply circuit to an intermediate voltage using a switching regulator of the switched mode power supply, in the pass-through operational mode, disabling the switching regulator such that the input voltage of the power supply circuit is unchanged by the switching regulator and an electric current consumption of the switching regulator approaches zero, and converting the intermediate voltage or the input voltage of the power supply circuit to an output voltage using a linear voltage regulator.

Abstract: A system and method for driving a relay circuit involves driving a relay circuit using a first driver circuit if a voltage of a battery supply for the relay circuit is lower than a voltage threshold and driving the relay circuit using a second driver circuit if the voltage of the battery supply for the relay circuit is higher than the voltage threshold.

Abstract: A power supply regulator circuit uses a feedback loop to control current through a first output transistor from a power supply input to a regulated power supply output. The first output transistor is included in an integrated circuit. In order to avoid heating of the integrated circuit in excess of an acceptable level due to permanent supply of a high current through the first transistor, current through a second output transistor in parallel with the first transistor, but outside the integrated circuit is raised when it is detected that the current through the first output transistor exceeds a threshold level. The second output transistor outside the integrated circuit serves to take over supply of a part of the power supply current from first output transistor inside integrated circuit, when long term supply of that part from first output transistor would lead to undesirable heating of the integrated circuit. During a limited time interval a first transistor current above the threshold level is acceptable.

Abstract: An electronic circuit has a signal conductor (11), a power supply reference conductor (10) connected by a switching circuit. The switching circuit contains a PMOS transistor (17) and an NMOS transistor realized on a common substrate (100). The NMOS transistor (17) has a source coupled to the power supply reference conductor (10). The NMOS transistor (18) has a source coupled to the drain of the PMOS transistor (17), and a drain coupled to the signal conductor (11). A control circuit (13, 14, 15, 16) switches between an “on” state and an “off” state, in which the control circuit (13, 14, 15, 16) controls the gate source voltages of the first and second MOS transistor (17, 18) to make channels of these MOS transistors (17, 18) conductive and not to make the channels of these first and second transistors (17, 18) conductive respectively. Preferably a complementary switching circuit is also provided.

Abstract: An integrated circuit has an input connection for connecting an external signal conductor that passes signals to execute functions in the device. The external signal conductor can pick up strong interfering signals with high frequency content, for example when the device is used in a car. To protect against unintended execution of functions the device contains a timer circuit comprising a capacitance and a current supplying circuit coupled to an integration node. A discharge diode is coupled between the input connection and the integration node, with a polarity such that the discharge diode, when in forward bias, is capable of draining current from the current supplying circuit. A detector is coupled to the integration node for generating a signal to be supplied to the integrated circuit device to respond to a signal transition on the conductor. The diode serves to reset integration on the integration node before the detector detects the transition in case of short pulses.

Abstract: Line driver for a LIN-bus. The line driver has a current source output transistor (T1) for pulling down the LIN-bus wire (LB) to ground (GND). The LIN-bus wire (LB) is connected to a positive supply voltage (VBAT) through a pull-up resistor (R1). The output transistor (T1) is driven by a driver stage (DRV) in response to an input current (J1) at an input node (X). The driver stage has a further resistor (R2) connected between the gate of the output transistor (T1) and a reference terminal (GND), a reference transistor (T2) which has its source connected to the reference terminal (GND) and its drain coupled to the input node (X); the gates of the output transistor (T1) and the reference transistor (T2) are connected to an output (DAO1) of a differential amplifier (DA1) which has an inverting input (DAN1) coupled to a bias voltage source (E2) and a non-inverting input (DAP1) coupled to the input node (X).

Abstract: Line driver for a LIN-bus. The line driver has a current source output transistor (T1) for pulling down the LIN-bus wire (LB) to ground (GND). The LIN-bus wire (LB) is connected to a positive supply voltage (VBAT) through a pull-up resistor (R1). The output transistor (T1) provides a ramp shaped output current under control of a ramp generator (RG). The ramp shaped output current in combination with the pull-up resistor (R1) asserts a ramp shaped output voltage on the LIN-bus wire (LB). According to the LIN-bus specifications the resistance of the pull-up resistor may vary between 500 Ohm and 1 kOhm. When the resistance is 1 kOhm, the output voltage is clamped to signal ground (GND) and a delay occurs between the edge in the data signal (TXD) and the corresponding rising ramp in the output voltage.

Abstract: Line driver for a LIN-bus. The line driver has a current source output transistor (T1) for pulling down the LIN-bus wire (LB) to ground (GND). The LIN-bus wire (LB) is connected to a positive supply voltage (VBAT) through a pull-up resistor (R1). The output transistor (T1) is driven by a driver stage (DRV) in response to an input current (J1) at an input node (X). The driver stage has a further resistor (R2) connected between the gate of the output transistor (T1) and a reference terminal (GND), a reference transistor (T2) which has its source connected to the reference terminal (GND) and its drain coupled to the input node (X); the gates of the output transistor (T1) and the reference transistor (T2) are connected to an output (DAO1) of a differential amplifier (DA1) which has an inverting input (DAN1) coupled to a bias voltage source (E2) and a non-inverting input (DAP1) coupled to the input node (X).

Abstract: Line driver for a LIN-bus. The line driver has a current source output transistor (T1) for pulling down the LIN-bus wire (LB) to ground (GND). The LIN-bus wire (LB) is connected to a positive supply voltage (VBAT) through a pull-up resistor (R1). The output transistor (T1) provides a ramp shaped output current under control of a ramp generator (RG). The ramp shaped output current in combination with the pull-up resistor (R1) asserts a ramp shaped output voltage on the LIN-bus wire (LB). According to the LIN-bus specifications the resistance of the pull-up resistor may vary between 500 Ohm and 1 kOhm. When the resistance is 1 kOhm, the output voltage is clamped to signal ground (GND) and a delay occurs between the edge in the data signal (TXD) and the corresponding rising ramp in the output voltage.