Abstract: A high-electron-mobility semiconductor device includes: a buffer region having first, second and third cross-sections forming a stepped lateral profile, the first cross-section being thicker than the third cross-section and comprising a first buried field plate disposed therein, the second cross-section interposed between the first and third cross-sections and forming oblique angles with the first and third cross-sections; and a barrier region of substantially uniform thickness extending along the stepped lateral profile of the buffer region, the barrier region being separated from the first buried field plate by a portion of the buffer region. The buffer region is formed by a first semiconductor material and the barrier region is formed by a second semiconductor material.

Abstract: In an embodiment, a semiconductor device includes a Group III-nitride-based High Electron Mobility Transistor (HEMT) configured as a bidirectional switch. The Group III nitride-based HEMT includes a first input/output electrode, a second input/output electrode, a gate structure arranged between the first input/output electrode and the second input/output electrode, and a field plate structure.

Abstract: There are disclosed herein various implementations of a III-Nitride bidirectional device. Such a bidirectional device includes a substrate, a back channel layer situated over the substrate, and a device channel layer and a device barrier layer situated over the back channel layer. The device channel layer and the device barrier layer are configured to produce a device two-dimensional electron gas (2DEG). In addition, the III-Nitride bidirectional device includes first and second gates formed on respective first and second depletion segments situated over the device barrier layer. The III-Nitride bidirectional device also includes a back barrier situated between the back channel layer and the device channel layer. A polarization of the back channel layer of the III-Nitride bidirectional device is substantially equal to a polarization of the device channel layer.

Abstract: A Group III-nitride-based enhancement mode transistor includes a multi-heterojunction fin structure. A first side face of the multi-heterojunction fin structure is covered by a first p-type Group III-nitride layer, and a second side face of the multi-heterojunction fin structure is covered by a second p-type Group III-nitride layer.

Abstract: In an embodiment, a semiconductor structure includes a support substrate comprising a surface adapted to support epitaxial growth of a Group III nitride, one or more epitaxial Group III nitride layers arranged on the surface and supporting a plurality of transistor devices assembled upon the support substrate, and a test structure formed in a Group III nitride layer. The test structure includes a plurality of trenches configured to provide an optical diffraction grating when illuminated by UV light. The trenches have a parameter corresponding to a parameter of a feature of the transistor devices.

Abstract: A semiconductor die includes a substrate and a semiconductor body supported by the substrate and having a periphery which is devoid of active devices and terminates at an edge face of the semiconductor die. The semiconductor body includes a first III-nitride semiconductor layer and a plurality of second III-nitride semiconductor layers below the first III-nitride semiconductor layer. An uninsulated connection structure extends vertically in the periphery of the semiconductor body and provides a vertical leakage path for at least some of the second III-nitride semiconductor layers to the substrate, to a metallization layer disposed above the substrate, or to both. A corresponding method of manufacturing the semiconductor die is also described.

Abstract: A high-electron-mobility field effect transistor is formed with a buffer region having a stepped lateral profile, the stepped lateral profile having first, second and third cross-sections of the buffer region, the first cross-section being thicker than the third cross-section and including a buried field plate, the second cross-section interposed between the first and third cross-sections and forming oblique angles with the first and third cross-sections. A barrier region is formed along the stepped lateral profile. The barrier region is separated from the buried field plate by a portion of the buffer region. The buffer region is formed from a first semiconductor material and the barrier region is formed from a second semiconductor material. The first and second semiconductor materials have different band-gaps such that an electrically conductive channel of a two-dimensional charge carrier gas arises at an interface between the buffer and barrier regions.

Abstract: In an embodiment, a method for evaluating a surface of a semiconductor substrate includes directing an incident light beam having multiple wavelengths at a position of a layer having a surface profile configured to form an optical diffraction grating, the layer including a Group III nitride, detecting a reflected beam, reflected from the position, and obtaining a spectrum of reflected intensity as a function of wavelength, the spectrum being representative of the surface profile of the position of the layer from which the beam is reflected, comparing the spectrum obtained from the detected beam with one or more reference spectra stored in memory, and estimating at least one parameter of the surface profile.

Abstract: A method includes providing a heterostructure body with a buffer region, and a barrier region disposed on the buffer region, and forming a gate structure for controlling the channel on the heterostructure body, the gate structure having a doped semiconductor region disposed on the heterostructure body, an interlayer disposed on the doped semiconductor region, and a gate electrode disposed on the interlayer. Forming the gate structure includes controlling a doping concentration of the doped semiconductor region such that a portion of the channel adjacent the gate structure is non-conductive at zero gate bias, and controlling electrical and geometrical characteristics of the interlayer based upon a relationship between the electrical and geometrical characteristics of the interlayer and corresponding effects on a static threshold voltage and a dynamic threshold voltage shift of the semiconductor device.

Abstract: In an embodiment, a method includes treating an edge region of a wafer including a substrate having an upper surface and one or more epitaxial Group III nitride layers arranged on the upper surface of the substrate, so as to remove material including at least one Group III element from the edge region.

Abstract: A semiconductor device includes a semiconductor body including a plurality of compound semiconductor layers and a two-dimensional charge carrier gas channel region formed in one of the compound semiconductor layers. The semiconductor device further includes a contact structure disposed in the semiconductor body. The contact structure includes a metal region and a doped region. The metal region extends into the semiconductor body from a first side of the semiconductor body to at least the compound semiconductor layer which includes the channel region. The doped region is formed in the semiconductor body between the metal region and the channel region so that the channel region is electrically connected to the metal region through the doped region.

Abstract: A Group III-nitride-based enhancement mode transistor having a heterojunction fin structure and a corresponding semiconductor device are described.

Abstract: There are disclosed herein various implementations of a III-Nitride bidirectional device. Such a bidirectional device includes a substrate, a back channel layer situated over the substrate, and a device channel layer and a device barrier layer situated over the back channel layer. The device channel layer and the device barrier layer are configured to produce a device two-dimensional electron gas (2DEG). In addition, the III-Nitride bidirectional device includes first and second gates formed on respective first and second depletion segments situated over the device barrier layer. The III-Nitride bidirectional device also includes a back barrier situated between the back channel layer and the device channel layer. A polarization of the back channel layer of the III-Nitride bidirectional device is substantially equal to a polarization of the device channel layer.

Abstract: In an embodiment, a semiconductor device includes a Group III-nitride-based High Electron Mobility Transistor (HEMT) configured as a bidirectional switch. The Group III nitride-based HEMT includes a first input/output electrode, a second input/output electrode, a gate structure arranged between the first input/output electrode and the second input/output electrode, and a field plate structure.

Abstract: In an embodiment, a switch circuit includes a bidirectional switch including a first input/output node, a second input/output node, a first diode and a second diode. The first diode and the second diode are coupled anti-serially between the first input/output node and the second input/output node.

Abstract: In an embodiment, an electronic device includes a semiconductor layer having a surface, a gate and a first current electrode on the surface and a dielectric layer extending between the gate and the first current electrode and including charged ions having a predetermined charge profile.

Abstract: A substrate having a buffer layer and a barrier layer is formed. The buffer and barrier layers have different bandgaps such that an electrically conductive channel comprising a two-dimensional charge carrier gas arises at an interface between the buffer and barrier layers due to piezoelectric effects. The substrate is placed in a fluorine containing gas mixture that includes free radical state fluorine particles and is substantially devoid of ionic state fluorine particles. A first lateral surface section of the substrate is exposed to the gas mixture such that the free radical state fluorine particles contact the first lateral surface section without penetrating the substrate. A semiconductor device that incorporates first lateral surface section in the structure of the device is formed in the substrate.

Abstract: A substrate having a buffer layer and a barrier layer is formed. The buffer and barrier layers have different bandgaps such that an electrically conductive channel comprising a two-dimensional charge carrier gas arises at an interface between the buffer and barrier layers due to piezoelectric effects. The substrate is placed in a fluorine containing gas mixture that includes free radical state fluorine particles and is substantially devoid of ionic state fluorine particles. A first lateral surface section of the substrate is exposed to the gas mixture such that the free radical state fluorine particles contact the first lateral surface section without penetrating the substrate. A semiconductor device that incorporates first lateral surface section in the structure of the device is formed in the substrate.

Abstract: A Group III-nitride-based enhancement mode transistor includes a multi-heterojunction fin structure. A first side face of the multi-heterojunction fin structure is covered by a first p-type Group III-nitride layer, and a second side face of the multi-heterojunction fin structure is covered by a second p-type Group III-nitride layer.

Abstract: In an embodiment, a semiconductor device includes a substrate, a Group III nitride-based semiconductor layer formed on the substrate, a first current electrode and a second current electrode formed on the Group III nitride-based semiconductor layer and spaced from each other, and a control electrode formed on the Group III nitride-based semiconductor layer between the first current electrode and the second current electrode. The control electrode includes at least a middle portion, configured to switch off a channel below the middle portion when a first voltage is applied to the control electrode, and second portions adjoining the middle portion. The second portions are configured to switch off a channel below the second portions when a second voltage is applied to the control electrode, the second voltage being less than the first voltage and the second voltage being less than a threshold voltage of the second portions.