Abstract: A method and system for extracting the parasitic capacitance in an IC and generating a technology file for at least one or more IC design tools are provided. Parasitic extraction using the preferred method can significantly reduce field solver computational intensity and save technology file preparation cycle time. The network-based technology file generation system enables circuit designers to obtain a desired technology file in a timely manner. The common feature of the various embodiments includes identifying common conductive feature patterns for a given technology generation. Capacitance models created from the identified patterns are used to assemble the required technology files for IC design projects using different technology node and different process flows.

Abstract: Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility.

Abstract: Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility.

Abstract: An integrated circuit (IC) design method includes providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data; generating an effective rectangle layout to represent the IC layout contour; and simulating the IC device using the effective rectangular layout.

Abstract: Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility.

Abstract: Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility.

Abstract: A de-coupling capacitor module using dummy conductive elements in an integrated circuit is disclosed. The de-coupling module comprises at least one circuit module having one or more active nodes, and at least one dummy conductive element unconnected to any active node, and separated from a high voltage conductor or a low voltage conductor by an insulation region to provide a de-coupling capacitance.

Abstract: Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility.

Abstract: A method involves providing a circuit pattern, generating a density report for the circuit pattern that identifies a feasible area for dummy insertion, simulating a planarization process with the density report and identifying a hot spot on the circuit pattern, inserting a virtual dummy pattern in the feasible area and adjusting the density report accordingly, and thereafter simulating the planarization process with the adjusted density until the hot spot is eliminated.

Abstract: A method is disclosed for utilizing mixed low threshold voltage (low-Vt) and high threshold voltage (high-Vt) devices in a cell-based design such that a tradeoff of both the circuit speed and power performance may be achieved. Using cells having non-uniform threshold devices for designing circuit, the speed or/and power optimization is comparable to fully custom designs.

Abstract: System and method for providing power to integrated circuitry with good power-on responsive time and reduced power-on transient glitches. A preferred embodiment comprises a daughter switch coupled to a circuit block, a first control circuit coupled to the daughter circuit, a second control circuit coupled to the first control circuit, and a mother circuit coupled to the circuit block and to the second control circuit. After the daughter switch is turned on by a control signal, the mother switch is not turned on until the daughter switch has discharged (charged) the voltage potential across power rails of the mother circuit to a point where glitches are minimized. The second control circuit turns on the mother circuit when the reduced voltage potential is reached, with a signal produced by the first control circuit reflects the voltage potential. Furthermore, a bypass circuit can be used to reduce leakage current.

Abstract: A system, method, and computer readable medium for generating a parameterized and characterized pattern library for use in extracting parasitics from an integrated circuit design is provided. In an embodiment, a layout of an interconnect pattern is provided. A process simulation may be performed on the interconnect pattern. In a further embodiment, the interconnect pattern is dissected into a plurality of segments taking into account OPC rules. A parasitic resistance and/or parasitic capacitance associated with the interconnect pattern may be determined by a physical model and/or field solver.

Abstract: A method for detection and scoring of hotspots in a design layout is provided. A plurality of indices is derived for a plurality of positions in the design layout. The plurality of indices comprises a first index sensitive to energy exposure of the design layout, a second index sensitive to process image formation, and a third index sensitive to mask manufacturing error. The plurality of indices is then analyzed to identify at least one hotspot in the design layout. The at least one hotspot is then prioritized using an integrated hotspot scoring system. The integrated hotspot scoring system prioritizes hotspots based on a look-up table approach or an interpolation approach.

Abstract: A method for processing an integrated circuit is provided. The method includes providing a first integrated circuit having a first scale, wherein the first integrated circuit comprises a shrinkable circuit comprising a first intellectual property (IP) layout, and a non-shrinkable circuit comprising a second IP layout; and generating a second integrated circuit having a second scale smaller than the first scale. The step of generating the second integrated circuit includes shrinking the shrinkable integrated circuit to the second scale. The method further includes merging the second IP layout with the non-shrinkable circuit to generate a final integrated circuit.

Abstract: An integrated circuit (IC) design method includes providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data; generating an effective rectangle layout to represent the IC layout contour; and simulating the IC device using the effective rectangular layout.

Abstract: A system, method, and computer readable medium for generating a parameterized and characterized pattern library for use in extracting parasitics from an integrated circuit design is provided. In an embodiment, a layout of an interconnect pattern is provided. A process simulation may be performed on the interconnect pattern. In a further embodiment, the interconnect pattern is dissected into a plurality of segments taking into account OPC rules. A parasitic resistance and/or parasitic capacitance associated with the interconnect pattern may be determined by a physical model and/or field solver.

Abstract: A de-coupling capacitor module using dummy conductive elements in an integrated circuit is disclosed. The de-coupling module comprises at least one circuit module having one or more active nodes, and at least one dummy conductive element unconnected to any active node, and separated from a high voltage conductor or a low voltage conductor by an insulation region to provide a de-coupling capacitance.

Abstract: A method and system for extracting the parasitic capacitance in an IC and generating a technology file for at least one or more IC design tools are provided. Parasitic extraction using the preferred method can significantly reduce field solver computational intensity and save technology file preparation cycle time. The network-based technology file generation system enables circuit designers to obtain a desired technology file in a timely manner. The common feature of the various embodiments includes identifying common conductive feature patterns for a given technology generation. Capacitance models created from the identified patterns are used to assemble the required technology files for IC design projects using different technology node and different process flows.

Abstract: System and method for providing power to integrated circuitry with good power-on responsive time and reduced power-on transient glitches. A preferred embodiment comprises a daughter switch coupled to a circuit block, a first control circuit coupled to the daughter circuit, a second control circuit coupled to the first control circuit, and a mother circuit coupled to the circuit block and to the second control circuit. After the daughter switch is turned on by a control signal, the mother switch is not turned on until the daughter switch has discharged (charged) the voltage potential across power rails of the mother circuit to a point where glitches are minimized. The second control circuit turns on the mother circuit when the reduced voltage potential is reached, with a signal produced by the first control circuit reflects the voltage potential. Furthermore, a bypass circuit can be used to reduce leakage current.

Abstract: A method for processing an integrated circuit is provided. The method includes providing a first integrated circuit having a first scale, wherein the first integrated circuit comprises a shrinkable circuit comprising a first intellectual property (IP) layout, and a non-shrinkable circuit comprising a second IP layout; and generating a second integrated circuit having a second scale smaller than the first scale. The step of generating the second integrated circuit includes shrinking the shrinkable integrated circuit to the second scale. The method further includes merging the second IP layout with the non-shrinkable circuit to generate a final integrated circuit.