Patents by Inventor Clinton Chao
Clinton Chao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11935842Abstract: Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 ?m, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.Type: GrantFiled: August 13, 2021Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shin-Puu Jeng, Clinton Chao, Szu-Wei Lu
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Publication number: 20210375789Abstract: Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 ?m, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.Type: ApplicationFiled: August 13, 2021Publication date: December 2, 2021Inventors: Shin-Puu Jeng, Clinton Chao, Szu-Wei Lu
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Patent number: 11094646Abstract: Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 ?m, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.Type: GrantFiled: April 22, 2019Date of Patent: August 17, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shin-Puu Jeng, Clinton Chao, Szu-Wei Lu
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Publication number: 20190252328Abstract: Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 ?m, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.Type: ApplicationFiled: April 22, 2019Publication date: August 15, 2019Inventors: Shin-Puu Jeng, Clinton Chao, Szu-Wei Lu
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Patent number: 10269730Abstract: Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 ?m, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.Type: GrantFiled: April 24, 2017Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shin-Puu Jeng, Clinton Chao, Szu-Wei Lu
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Publication number: 20170229403Abstract: Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 ?m, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.Type: ApplicationFiled: April 24, 2017Publication date: August 10, 2017Inventors: Shin-Puu Jeng, Clinton Chao, Szu-Wei Lu
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Patent number: 9633954Abstract: Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 ?m, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.Type: GrantFiled: February 29, 2016Date of Patent: April 25, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shin-Puu Jeng, Clinton Chao, Szu Wei Lu
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Publication number: 20160181209Abstract: Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 ?m, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.Type: ApplicationFiled: February 29, 2016Publication date: June 23, 2016Inventors: Shin-Puu Jeng, Clinton Chao, Szu Wei Lu
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Patent number: 9275948Abstract: Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 ?m, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.Type: GrantFiled: December 28, 2012Date of Patent: March 1, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shin-Puu Jeng, Clinton Chao, Szu Wei Lu
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Patent number: 8945998Abstract: Various structures of a programmable semiconductor interposer for electronic packaging are described. An array of semiconductor devices having various values is formed in the interposer. A user can program the interposer and form a “virtual” device having a desired value by selectively connecting various one of the array of devices to contact pads formed on the surface of the interposer. An inventive electronic package structure includes a standard interposer having an array of unconnected devices of various values and a device selection unit, which selectively connects various one of the array of devices in the standard interposer to an integrated circuit die encapsulated in the electronic package. Methods of forming the programmable semiconductor interposer and the electronic package are also illustrated.Type: GrantFiled: July 1, 2013Date of Patent: February 3, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Shun Hsu, Clinton Chao, Mark Shane Peng
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Patent number: 8704383Abstract: A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 ?m. A plurality of traces is formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. A semiconductor chip may be mounted on the solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.Type: GrantFiled: April 20, 2012Date of Patent: April 22, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Szu-Wei Lu, Clinton Chao, Ann Luh, Tjandra Winata Karta, Jerry Tzou, Kuo-Chin Chang
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Publication number: 20130295727Abstract: Various structures of a programmable semiconductor interposer for electronic packaging are described. An array of semiconductor devices having various values is formed in the interposer. A user can program the interposer and form a “virtual” device having a desired value by selectively connecting various one of the array of devices to contact pads formed on the surface of the interposer. An inventive electronic package structure includes a standard interposer having an array of unconnected devices of various values and a device selection unit, which selectively connects various one of the array of devices in the standard interposer to an integrated circuit die encapsulated in the electronic package. Methods of forming the programmable semiconductor interposer and the electronic package are also illustrated.Type: ApplicationFiled: July 1, 2013Publication date: November 7, 2013Inventors: Chao-Shun Hsu, Clinton Chao, Mark Shane Peng
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Patent number: 8551813Abstract: A wafer level integrated circuit assembly method is conducted as follows. First, a mother device wafer with plural first posts is provided. The first posts are used for electrical connection and are made of copper according to an embodiment. Solder is sequentially formed on the first posts. The solder is preferably pre-formed on a wafer, and the locations of the solder correspond to the first posts of the mother device wafer. Consequently, the solder can be formed on or adhered to the first posts by placing the wafer having pre-formed solder onto the first posts. Plural dies having plural second posts corresponding to the first posts are placed onto the mother device wafer. Then, the solder is reflowed to bond the first and second posts, and the mother device wafer is diced.Type: GrantFiled: July 20, 2012Date of Patent: October 8, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien Hsiun Lee, Clinton Chao, Mirng Ji Lii, Tjandra Winata Karta
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Patent number: 8476735Abstract: Various structures of a programmable semiconductor interposer for electronic packaging are described. An array of semiconductor devices having various values is formed in the interposer. A user can program the interposer and form a “virtual” device having a desired value by selectively connecting various one of the array of devices to contact pads formed on the surface of the interposer. An inventive electronic package structure includes a standard interposer having an array of unconnected devices of various values and a device selection unit, which selectively connects various one of the array of devices in the standard interposer to an integrated circuit die encapsulated in the electronic package. Methods of forming the programmable semiconductor interposer and the electronic package are also illustrated.Type: GrantFiled: May 29, 2007Date of Patent: July 2, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Shun Hsu, Clinton Chao, Mark Shane Peng
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Patent number: 8426256Abstract: A method of forming a stacked die structure is disclosed. A plurality of dies are respectively bonded to a plurality of semiconductor chips on a first surface of a wafer. An encapsulation structure is formed over the plurality of dies and the first surface of the wafer. The encapsulation structure covers a central portion of the first surface of the wafer and leaves an edge portion of the wafer exposed. A protective material is formed over the first surface of the edge portion of the wafer.Type: GrantFiled: February 5, 2010Date of Patent: April 23, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: C. W. Hsiao, Bo-I Lee, Tsung-Ding Wang, Kai-Ming Ching, Chen-Shien Chen, Chien-Hsiun Lee, Clinton Chao
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Patent number: 8367474Abstract: Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 ?m, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.Type: GrantFiled: January 4, 2011Date of Patent: February 5, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shin-Puu Jeng, Clinton Chao, Szu Wei Lu
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Patent number: 8334170Abstract: A method for fabricating a semiconductor device is provided which includes providing a first device, a second device, and a third device, providing a first coating material between the first device and the second device, the first coating material being uncured, providing a second coating material between the second device and the third device, the second coating material being uncured, and thereafter, curing the first and second coating materials in a same process.Type: GrantFiled: June 27, 2008Date of Patent: December 18, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Dean Wang, Chien-Hsiun Lee, Chen-Shien Chen, Clinton Chao, Mirng-Ji Lii, Tjandra Winata Karta
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Publication number: 20120288998Abstract: A wafer level integrated circuit assembly method is conducted as follows. First, a mother device wafer with plural first posts is provided. The first posts are used for electrical connection and are made of copper according to an embodiment. Solder is sequentially formed on the first posts. The solder is preferably pre-formed on a wafer, and the locations of the solder correspond to the first posts of the mother device wafer. Consequently, the solder can be formed on or adhered to the first posts by placing the wafer having pre-formed solder onto the first posts. Plural dies having plural second posts corresponding to the first posts are placed onto the mother device wafer. Then, the solder is reflowed to bond the first and second posts, and the mother device wafer is diced.Type: ApplicationFiled: July 20, 2012Publication date: November 15, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien Hsiun Lee, Clinton Chao, Mirng Ji Lii, Tjandra Winata Karta
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Patent number: 8247267Abstract: A wafer level integrated circuit assembly method is conducted as follows. First, a mother device wafer with plural first posts is provided. The first posts are used for electrical connection and are made of copper according to an embodiment. Solder is sequentially formed on the first posts. The solder is preferably pre-formed on a wafer, and the locations of the solder correspond to the first posts of the mother device wafer. Consequently, the solder can be formed on or adhered to the first posts by placing the wafer having pre-formed solder onto the first posts. Plural dies having plural second posts corresponding to the first posts are placed onto the mother device wafer. Then, the solder is reflowed to bond the first and second posts, and the mother device wafer is diced.Type: GrantFiled: March 11, 2008Date of Patent: August 21, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien Hsiun Lee, Clinton Chao, Mirng Ji Lii, Tjandra Winata Karta
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Publication number: 20120199974Abstract: A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 ?m. A plurality of traces is formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. A semiconductor chip may be mounted on the solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.Type: ApplicationFiled: April 20, 2012Publication date: August 9, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Szu Wei Lu, Clinton Chao, Ann Luh, Tjandra Winata Karta, Jerry Tzou, Kuo-Chin Chang