Abstract: A method of forming an integrated circuit structure is provided. The method includes providing an interposer wafer; mounting the interposer wafer onto a handling wafer; thinning a backside of the interposer wafer; removing the handling wafer from the interposer wafer after the step of thinning; securing the interposer wafer on a fixture; and bonding a die on the interposer wafer.

Abstract: A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 ?m. A plurality of traces are formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. A semiconductor chip may be mounted on the solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.

Abstract: A method of packaging integrated circuit structures is provided. The method includes providing a wafer having bonding conductors on a surface of the wafer, and applying a compound underfill onto the surface of the wafer. The compound underfill includes an underfill material and a flux material. A die is then bonded on the wafer after the step of applying the compound underfill, wherein solder bumps on the die are joined with the bonding conductors.

Abstract: Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 ?m, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.

Abstract: Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 ?m, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.

Abstract: A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 ?m. A plurality of traces are formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. A semiconductor chip may be mounted on the solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.

Abstract: A method of forming a stacked die structure is disclosed. A plurality of dies are respectively bonded to a plurality of semiconductor chips on a first surface of a wafer. An encapsulation structure is formed over the plurality of dies and the first surface of the wafer. The encapsulation structure covers a central portion of the first surface of the wafer and leaves an edge portion of the wafer exposed. A protective material is formed over the first surface of the edge portion of the wafer.

Abstract: A through-silicon via (TSV) enabled twisted pair is provided. A pair of complementary conductive lines is provided as a twisted pair. Each of the conductive lines of the twisted pair is formed by alternating conductive sections on opposing sides of a substrate. The alternating conductive sections are electrically coupled by at least in part a TSV. The conductive lines overlap or are entwined such the point at which the conductive lines cross, the conductive lines are on opposing sides of the substrate. The conductive lines are weaved in this manner for the length of the conductive trace.

Abstract: A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 ?m. A plurality of through-hole vias are formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.

Abstract: A method for forming a single die includes forming at least one first active device over a first substrate and at least one first metallic layer coupled to the first active device. At least one second metallic layer is formed over a second substrate, wherein the second substrate does not include any active device. The at least one first metallic layer is bonded with the at least one second metallic layer such that the first substrate and the second substrate constitute a single die.

Abstract: A system and a method of testing a semiconductor die is provided. An embodiment comprises a plurality of tips that each comprise a substrate with a conductive via, a first dielectric layer with vias connected to the conductive via, a second dielectric layer with vias over the first dielectric layer, and a metal layer over the second dielectric layer. Additional dielectric layers with vias may be used. This tip is electrically connected to a redistribution line that routes signals between the tip to electrical connections on a space transformation layer. The space transformation layer is electrically connected to a printed circuit board using, for example, a spring loaded connection such as a pogo pin. The space transformation layer is aligned onto the printed circuit board by a series of guidance mechanisms such as guide pins or smooth fixtures, and the planarity of the tips is adjusted by adjusting the screws.

Abstract: A system and a method of testing a semiconductor die is provided. An embodiment comprises a plurality of metal tips that are connected to a redistribution layer that fans out the pitch from the tips to metal plugs located in the substrate. The metal tips could be formed using semiconductor processes and either adding smaller layers of metal to larger layers of metal or else removing portions of one piece of metal to form the tips. The metal plugs are connected to a space transformation layer. The space transformation layer is electrically connected to a printed circuit board using, for example, a spring loaded connection such as a pogo pin. The space transformation layer is aligned onto the printed circuit board by a series of guidance mechanisms such as smooth fixtures, and the planarity of the tips is adjusted by adjusting a series of screws.

Abstract: A method for fabricating a semiconductor device is provided which includes providing a first device, a second device, and a third device, providing a first coating material between the first device and the second device, the first coating material being uncured, providing a second coating material between the second device and the third device, the second coating material being uncured, and thereafter, curing the first and second coating materials in a same process.

Abstract: A through-silicon via (TSV) enabled twisted pair is provided. A pair of complementary conductive lines is provided as a twisted pair. Each of the conductive lines of the twisted pair is formed by alternating conductive sections on opposing sides of a substrate. The alternating conductive sections are electrically coupled by at least in part a TSV. The conductive lines overlap or are entwined such the point at which the conductive lines cross, the conductive lines are on opposing sides of the substrate. The conductive lines are weaved in this manner for the length of the conductive trace.

Abstract: A wafer level integrated circuit assembly method is conducted as follows. First, a mother device wafer with plural first posts is provided. The first posts are used for electrical connection and are made of copper according to an embodiment. Solder is sequentially formed on the first posts. The solder is preferably pre-formed on a wafer, and the locations of the solder correspond to the first posts of the mother device wafer. Consequently, the solder can be formed on or adhered to the first posts by placing the wafer having pre-formed solder onto the first posts. Plural dies having plural second posts corresponding to the first posts are placed onto the mother device wafer. Then, the solder is reflowed to bond the first and second posts, and the mother device wafer is diced.

Abstract: A semiconductor package structure and the methods for forming the same are provided. The semiconductor package structure includes an interposer; a first plurality of bonding pads on a side of the interposer; a semiconductor chip; and a second plurality of bonding pads on a side of the semiconductor chip. The first and the second plurality of bonding pads are bonded through metal-to-metal bonds.

Abstract: SiP design systems and methods. The system comprises a system partitioning module, a subsystem integration module, a physical design module, and an analysis module. The system partitioning module partitions a target system into subsystem partitions according to partition criteria. The subsystem integration module generates an architecture design and/or a cost estimation for the target system according to the subsystem partitions, at least one SiP platform, and IC geometry data. The physical design module generates a SiP physical design with physical routing for the target system according to the architecture design, the subsystem partitions, the SiP platform, and the IC geometry data. The analysis module performs a performance check within the subsystem partitions based on the SiP physical design and/or simulations of the target system.

Abstract: A semiconductor device and method of manufacturing are provided that include forming an electrically conductive bump on a substrate and forming at least one passivation layer on the bump to reduce solder joint failures.

Abstract: A stacked structure includes a first die coupled to a first substrate and having a first conductive structure formed through the first die. A second die is mounted over the first die. The second die is coupled to the first substrate by the first conductive structure. At least one first support structure formed from a second substrate is provided over the first substrate, adjacent to at least one of the first die and the second die. A top surface of the first support structure is substantially coplanar with a top surface of at least one of the first and second dies adjacent to the first support structure. The stacked structure further includes a heat spreader mounted over the second die.

Abstract: A semiconductor structure includes a first semiconductor die and a second semiconductor die identical to the first semiconductor die. The first semiconductor die includes a first identification circuit; and a first plurality of input/output (I/O) pads on the surface of the first semiconductor die. The second semiconductor die includes a second identification circuit, wherein the first and the second identification circuits are programmed differently from each other; and a second plurality of I/O pads on the surface of the second semiconductor die. Each of the first plurality of I/O pads is vertically aligned to and connected to one of the respective second plurality of I/O pads. The second semiconductor die is vertically aligned to and bonded on the first semiconductor die.