Patents by Inventor COLIN A. MACDONALD

COLIN A. MACDONALD has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8607206
    Abstract: A computer-implemented method of generating output computer code, for an application executable via a server running application logic in communication with a client running a presentation layer for the application, from input computer code of a synchronous application in which logic and presentation layers run locally on a single computer. The output code runs asynchronously.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: December 10, 2013
    Assignee: GROUP Business Software AG
    Inventors: Nathan T. Freeman, Colin Macdonald, Tim Tripcony
  • Publication number: 20130073209
    Abstract: Systems and methods for positioning horizontal wells within a limited-pre-defined boundary. The systems and methods include an automated process for creating jointed target pairs or horizontal laterals to be utilized for planning horizontal wells in order to position the horizontal laterals within limited pre-defined boundary(ies).
    Type: Application
    Filed: March 15, 2010
    Publication date: March 21, 2013
    Inventors: Dan Colvin, Gary Daniel Schottle, Colin MacDonald, Philip William Woodard
  • Publication number: 20120079463
    Abstract: A computer-implemented method of generating output computer code, for an application executable via a server running application logic in communication with a client running a presentation layer for the application, from input computer code of a synchronous application in which logic and presentation layers run locally on a single computer. The output code runs asynchronously.
    Type: Application
    Filed: September 26, 2011
    Publication date: March 29, 2012
    Applicant: GROUP BUSINESS SOFTWARE AG
    Inventors: Nathan T. Freeman, Colin MaCdonald, Tim Tripcony
  • Publication number: 20110246535
    Abstract: A database abstraction layer provides structured access to an unstructured database. The database abstraction layer imposes a relational structure on the otherwise unstructured data, so the data may be accessed as though it were stored in a relational database.
    Type: Application
    Filed: January 14, 2011
    Publication date: October 6, 2011
    Applicant: GROUP BUSINESS SOFTWARE AG
    Inventors: Nathan T. Freeman, Colin Macdonald, Tim Tripcony, Luz Londono, Jennifer Meade
  • Patent number: 7716511
    Abstract: A method includes determining a first operational characteristic representative of an operational speed of a circuit device at a first time. The method further includes receiving an input signal at an input of a first latch of the circuit device and receiving an output signal at an input of a second latch of the circuit device. The method additionally includes delaying a clock signal by a first delay to provide a first adjusted clock signal and delaying the clock signal by a second delay to provide a second adjusted clock signal. In one embodiment, the first delay and the second delay are based on the first operational characteristic. The method further includes latching the input signal at the first latch responsive to the first adjusted clock signal and latching the output signal at the second latch responsive to the second adjusted clock signal.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: May 11, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Anis M. Jarrar, Colin MacDonald
  • Patent number: 7420401
    Abstract: An integrated circuit is configured with a pin for specifying a reset configuration vector of a circuitry within the integrated circuit. The resistance value of a low cost external resistor coupled to the pin is detected and utilized to identify the configuration. Logic on the integrated circuit detects and utilizes the resistor value to index to a configuration vector in a look-up table. The integrated circuit is then configured in accordance with the indexed configuration vector.
    Type: Grant
    Filed: June 14, 2006
    Date of Patent: September 2, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Colin MacDonald, Alan J. Carlin, Chris C. Dao
  • Patent number: 7418675
    Abstract: A system an method of designing an integrated circuit identifies a plurality of synchronous cells of an integrated circuit to be driven by a clock driver, wherein the plurality of synchronous cells are a subset of previously placed cells of the integrated circuit. The placement of synchronous cells is performed to reduce a current needed from the clock driver to drive the plurality of synchronous cells.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: August 26, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Colin MacDonald, John M. Dalbey, Anis M. Jarrar
  • Patent number: 7378993
    Abstract: A method and system for transmitting binary-coded data use partitioning of data words in a plurality of data nibbles. The data nibbles are coded using modified a 1-bit hot coding format that transforms a data nibble in a data segment including a plurality of bit groups. A change in a digital state at a bit position in a more significant bit group is maintained at that bit position in less significant bit groups, and information is transmitted in a form of a transition between digital states. The data segments are transmitted in phases each including one bit group from each data segment. At a receiving terminal, the bit groups are converted back in the binary-coded data words. In one application, the invention is used to reduce power consumption during data transmissions to and from an integrated circuit device.
    Type: Grant
    Filed: January 4, 2007
    Date of Patent: May 27, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Colin MacDonald, Alan J. Carlin, Donald L. Tietjen
  • Publication number: 20070290731
    Abstract: An integrated circuit is configured with a pin for specifying a reset configuration vector of a circuitry within the integrated circuit. The resistance value of a low cost external resistor coupled to the pin is detected and utilized to identify the configuration. Logic on the integrated circuit detects and utilizes the resistor value to index to a configuration vector in a look-up table. The integrated circuit is then configured in accordance with the indexed configuration vector.
    Type: Application
    Filed: June 14, 2006
    Publication date: December 20, 2007
    Inventors: Colin MacDonald, Alan J. Carlin, Chris C. Dao
  • Publication number: 20070214377
    Abstract: A method includes determining a first operational characteristic representative of an operational speed of a circuit device at a first time. The method further includes receiving an input signal at an input of a first latch of the circuit device and receiving an output signal at an input of a second latch of the circuit device. The method additionally includes delaying a clock signal by a first delay to provide a first adjusted clock signal and delaying the clock signal by a second delay to provide a second adjusted clock signal. In one embodiment, the first delay and the second delay are based on the first operational characteristic. The method further includes latching the input signal at the first latch responsive to the first adjusted clock signal and latching the output signal at the second latch responsive to the second adjusted clock signal.
    Type: Application
    Filed: March 8, 2006
    Publication date: September 13, 2007
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Anis Jarrar, Colin MacDonald
  • Publication number: 20070180410
    Abstract: A system an method of designing an integrated circuit identifies a plurality of synchronous cells of an integrated circuit to be driven by a clock driver, wherein the plurality of synchronous cells are a subset of previously placed cells of the integrated circuit. The placement of synchronous cells is performed to reduce a current needed from the clock driver to drive the plurality of synchronous cells.
    Type: Application
    Filed: January 30, 2006
    Publication date: August 2, 2007
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Colin MacDonald, John Dalbey, Anis Jarrar
  • Patent number: 6999627
    Abstract: Embodiments of the present invention relate to deterministic prediction in an image processing system. One aspect relates to an image processing system having a deterministic prediction decode unit for predicting individual pixels of an image based on a predetermined deterministic prediction algorithm. The deterministic prediction decode unit includes a look-up table, organized into four spatial phases, for storing values to be used by the predetermined deterministic prediction algorithm when converting a relatively low resolution image to a relatively higher resolution image. A prediction is made for a target pixel by accessing at least two of the four spatial phases of the look-up table to read at least two possible values of the target pixel. In one embodiment, the value of two target pixels can be provided within a same clock period, thus allowing for the decoding of two spatial phases with each access to the look-up table.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: February 14, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Colin MacDonald, Tamas Kovacs
  • Patent number: 6763150
    Abstract: A circuit for processing a first image including two image supply blocks, two image processing units, a control unit and a plurality of buses. The image supply blocks assert selected lines of image data onto a respective one of first and second plurality of buses. The image processing units each process the data according to respective algorithms and provide respective update ok signals that each indicate that the respective image processing unit has completed use of the first sub-portion of data. The image supply blocks provide respective update signals to the image processing units in response to the update ok signals from both of the image processing units, transfer data from the second sub-portion to the first, and assert new data on the second sub-portion. Each image processing unit, in response to receiving both update signals, changes state to track the data without losing bus cycles to maintain performance.
    Type: Grant
    Filed: August 29, 2000
    Date of Patent: July 13, 2004
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Colin MacDonald
  • Publication number: 20030113023
    Abstract: Embodiments of the present invention relate to deterministic prediction in an image processing system. One aspect relates to an image processing system having a deterministic prediction decode unit for predicting individual pixels of an image based on a predetermined deterministic prediction algorithm. The deterministic prediction decode unit includes a look-up table, organized into four spatial phases, for storing values to be used by the predetermined deterministic prediction algorithm when converting a relatively low resolution image to a relatively higher resolution image. A prediction is made for a target pixel by accessing at least two of the four spatial phases of the look-up table to read at least two possible values of the target pixel. In one embodiment, the value of two target pixels can be provided within a same clock period, thus allowing for the decoding of two spatial phases with each access to the look-up table.
    Type: Application
    Filed: December 19, 2001
    Publication date: June 19, 2003
    Inventors: Colin MacDonald, Tamas Kovacs
  • Patent number: 6279083
    Abstract: A memory controller (26) compares the current address and the previous address sent by a microprocessor (12). If the addresses are DRAM addresses and the current row address matches the previous row address, i.e. same DRAM page access, then the memory controller disables caching (28) of the same DRAM page access. The same DRAM page access disables caching because the same DRAM page access is not substantially longer than a cache access. A counter (50) and comparator (52) allows the memory controller to hold off some number of same DRAM page accesses before disabling caching to give time for the memory controller to set up to the new page.
    Type: Grant
    Filed: March 24, 1999
    Date of Patent: August 21, 2001
    Assignee: Motorola, Inc.
    Inventor: Colin MacDonald