Abstract: A microelectronic device comprises a stack structure, a staircase structure, a first liner material, a liner structure, conductive contact structures, and barrier structures. The stack structure comprises vertically alternating conductive structures and insulative structures arranged in tiers. Each of the tiers individually comprises one of the conductive structures and one of the insulative structures. The staircase structure has steps comprising edges of at least some of the tiers of the stack structure. The first liner material is on the steps of the staircase structure, and the liner structure on the first liner material. The conductive contact structures extend through the first liner material and the liner structure and to the conductive structures of the stack structure. The barrier structures are between the conductive contact structures and the liner structure and vertically span substantially the same tiers of the stack structure as the liner structure.

Abstract: Electronic devices comprising a doped dielectric material adjacent to a source contact, tiers of alternating conductive materials and dielectric materials adjacent to the doped dielectric material, and pillars extending through the tiers, the doped dielectric material, and the source contact and into the source stack. Related methods and electronic systems are also disclosed.

Abstract: A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers, with the stack extending from a memory-array region into a stair-step region. The stair-step region comprises a flight of stairs in a first vertical cross-section along a first direction. Masking material is formed directly above the flight of stairs. A species is ion implanted into the masking material to form different-composition first and second regions that are directly above individual of the stairs along a second direction that is orthogonal to the first direction. One of the first and the second regions is removed selectively relative to the other of the first and the second regions.

Abstract: Devices and methods are disclosed, including transistors, semiconductor devices and systems. Example semiconductor devices and methods include interconnect structures with lateral isolation structures around a vertical conductor. Devices and methods are shown where the isolation structures are located with a staircase configuration in a memory device with an array of vertical memory strings.

Abstract: A method used in forming memory circuitry comprising strings of memory cells comprising channel-material strings comprises forming a stack comprising vertically-alternating first tiers and second tiers. The first tiers are conductive and the second tiers are insulative at least in a finished-circuitry construction. A first set of horizontally-spaced pairs of channel-material strings are formed to extend through the first tiers and the second tiers. After forming the first set, a second set of horizontally-spaced pairs of channel-material strings is formed to extend through the first tiers and the second tiers. The pairs in the first set individually horizontally alternating with the pairs in the second set. Other embodiments, including structure, are disclosed.

Abstract: Integrated circuitry comprises a stack comprising vertically-alternating insulative tiers and conductive tiers that extend from an array region into a stair-step region. The stair-step region comprises a flight of stairs that comprise treads that individually comprise a target conductive tier. A conductive via extends from directly above, through, and to directly below one of the individual treads to a bottom of the stack. It comprises conductor material that is directly electrically coupled to conductive material that is in the target conductive tier of the one individual tread. The conductive material that is in the target conductive tier of the one individual tread extends upwardly and downwardly from the target conductive tier of the one individual tread and is aside and directly against sidewalls of the conductor material of the conductive via directly above and directly below the target conductive tier of the one individual tread. Other embodiments, including method, are disclosed.

Abstract: A method used in forming memory circuitry comprising strings of memory cells comprising channel-material strings comprises forming a stack comprising vertically-alternating first tiers and second tiers. The first tiers are conductive and the second tiers are insulative at least in a finished-circuitry construction. A first set of horizontally-spaced pairs of channel-material strings are formed to extend through the first tiers and the second tiers. After forming the first set, a second set of horizontally-spaced pairs of channel-material strings is formed to extend through the first tiers and the second tiers. The pairs in the first set individually horizontally alternating with the pairs in the second set. Other embodiments, including structure, are disclosed.

Abstract: Integrated circuitry comprises a stack comprising vertically-alternating insulative tiers and conductive tiers that extend from an array region into a stair-step region. Individual treads of the stairs comprise conductive material of one of the conductive tiers. A conductive via extends from directly above, through, and to directly below one of the individual treads to a bottom of the stack. The conductive via comprises conductor material that is directly electrically coupled to conductive material of the target conductive tier of the one individual tread. The conductive material of the target conductive tier of the one individual tread is not directly above the conductive material that is in the conductive tier that is immediately-below the one individual tread. Other embodiments, including method, are disclosed.

Abstract: Integrated circuitry comprises a stack comprising vertically-alternating insulative tiers and conductive tiers that extend from an array region into a stair-step region. The stair-step region comprises a flight of stairs that comprise treads, with individual of the treads comprising a target conductive tier. A conductive via extends from directly above, through, and to directly below one of the individual treads to a bottom of the stack. The conductive via comprises conductor material that is directly electrically coupled to the conductive material that is in the target conductive tier of the one individual tread. The conductor material is in the target conductive tier directly above and directly below the conductive material that is in the target conductive tier. Other embodiments, including method, are disclosed.

Abstract: Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, a memory device includes a vertically-oriented contact pillar and a tiered structure proximate to the vertically-oriented contact pillar. The tiered structure includes an access line between two insulative layers and insulative fill structure. The insulative fill structure includes a tapered portion that is between the vertically-oriented contact pillar and the access line. The tapered portion may be between facing surfaces of ends of the insulative layers.

Abstract: Some embodiments include a method of forming an assembly (e.g., a memory array). A first opening is formed through a stack of alternating first and second levels. The first levels contain silicon nitride, and the second levels contain silicon dioxide. Some of the silicon dioxide of the second levels is replaced with memory cell structures. The memory cell structures include charge-storage regions adjacent charge-blocking regions. Tunneling material is formed within the first opening, and channel material is formed adjacent the tunneling material. A second opening is formed through the stack. The second opening extends through remaining portions of the silicon dioxide, and through the silicon nitride. The remaining portions of the silicon dioxide are removed to form cavities. Conductive regions are formed within the cavities. The silicon nitride is removed to form voids between the conductive regions. Some embodiments include memory arrays.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating different-composition first tiers and second tiers. The stack comprises lower channel-material strings extending through the first tiers and the second tiers. A sacrificial plug comprises sacrificial material directly above individual of the lower channel-material strings. The sacrificial material is removed from laterally-opposing corner regions of the sacrificial plug in a greater amount diagonally than orthogonally relative to a sidewall of individual of the corner regions and than orthogonally relative to a top of the individual corner regions. Insulator material is formed in void spaces left from the removing. After forming the insulator material, remaining volume of the sacrificial plug is removed.

Abstract: A memory array comprising strings of memory cells comprises a conductor tier comprising conductor material. Laterally-spaced memory blocks individually comprise a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Conducting material of a lower of the conductive tiers directly electrically coupling together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. The conducting material in the lower conductive tier comprises upper conductively-doped semiconductive material, lower conductively-doped semiconductive material, and intermediate material vertically there-between.

Abstract: Integrated circuitry comprises a stack comprising vertically-alternating insulative tiers (comprising first insulative material) and conductive tiers that extend from an array region into a stair-step region. The stair-step region comprises a flight of stairs (comprising treads) within a cavity. Individual treads comprise a target conductive tier. Conductive vias individually extend downwardly from and directly below the individual treads to circuitry that is directly below the stack. The conductive vias comprise conductor material that directly electrically couples together conductive material of the target conductive tier of the individual treads and the circuitry that is directly below the stack. Second insulative material is in and fills a majority of volume of the cavity that is between the conductive vias in a vertical cross-section.

Abstract: Systems, methods, and apparatus are provided for substrate isolation in a three-dimensional (3D) memory array. The 3D array of vertically stacked memory cells formed on a substrate, the vertically stacked memory cells having horizontally oriented access devices and storage nodes can include a first portion of a digit line liner formed on the substrate, a second portion of the digit line liner formed on the substrate, and a dielectric material having a portion formed between the first portion of the digit line liner and the second portion of the digit line liner and the substrate.

Abstract: A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers, with the stack extending from a memory-array region into a stair-step region. The stair-step region comprises a flight of stairs in a first vertical cross-section along a first direction. Masking material is formed directly above the flight of stairs. A species is ion implanted into the masking material to form different-composition first and second regions that are directly above individual of the stairs along a second direction that is orthogonal to the first direction. One of the first and the second regions is removed selectively relative to the other of the first and the second regions.

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory-blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above conductor material of a conductor tier. Channel-material-string constructions extend through the insulative and conductive tiers to a lowest of the conductive tiers. The channel-material-string constructions comprise a charge-blocking-material string, a storage-material string laterally-inward of the charge-blocking-material string, a charge-passage-material string laterally-inward of the storage-material string, and a channel-material string laterally-inward of the charge-passage-material string. A lowest surface of the charge-blocking-material string that is above a lowest surface of the lowest conductive tier is below a lowest surface of a lowest of the insulative tiers that is immediately-above the lowest conductive tier.

Abstract: A microelectronic device includes a stack structure comprising a vertically alternating sequence of insulative and conductive structures arranged in tiers. At least one pillar, comprising a channel material, extends through the stack structure. A source region, below the stack structure, comprises a doped material with vertical extensions that protrude to an interface with the channel material at an elevation proximate at least one source-side GIDL region. Slit structures extend through the stack structure to divide the structure into blocks of pillar arrays. A series of spaced, discrete pedestal structures are included along a base of the slit structures. Forming the microelectronic device structure may include forming a lateral opening through cell materials of the pillar, vertically recessing the channel material, and laterally recessing other material(s) of the pillar before forming the doped material in the broadened recesses.

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above conductor material of a conductor tier. Channel-material-string constructions extend through the insulative and conductive tiers to a lowest of the conductive tiers. The channel-material-string constructions individually comprise a charge-blocking-material string, a storage-material string laterally-inward of the charge-blocking-material string, a charge-passage-material string laterally-inward of the storage-material string, and a channel-material string laterally-inward of the charge-passage-material string. Conductive material in the lowest conductive tier directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier.

Abstract: A memory array comprising strings of memory cells comprises a conductor tier comprising conductor material. Laterally-spaced memory blocks individually comprise a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Conducting material of a lower of the conductive tiers directly electrically coupling together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. The conducting material in the lower conductive tier comprises upper conductively-doped semiconductive material, lower conductively-doped semiconductive material, and intermediate material vertically there-between.