Abstract: A method for manufacturing an optical sensor is provided. The operations of the method for manufacturing the optical sensor includes providing a semiconductive layer having an electrical circuit area and an optical sensing area; forming a first electrical contact directly over the electrical circuit area; forming a first light guiding part directly over the optical sensing area simultaneously with forming the first electrical contact; forming a first metal layer directly over the first electrical contact; forming a second light guiding part directly over the first light guiding part simultaneously with forming a second electrical contact directly over the first electrical contact; forming a thick metal layer over the electrical circuit area and an optical sensing area; and forming an aperture in the thick metal layer, wherein the aperture aligning with the optical sensing area.

Abstract: A method for manufacturing an optical sensor is provided. The operations of the method for manufacturing the optical sensor includes providing a semiconductive layer having an electrical circuit area and an optical sensing area; forming a first electrical contact directly over the electrical circuit area; forming a first light guiding part directly over the optical sensing area simultaneously with forming the first electrical contact; forming a first metal layer directly over the first electrical contact; forming a second light guiding part directly over the first light guiding part simultaneously with forming a second electrical contact directly over the first electrical contact; forming a thick metal layer over the electrical circuit area and an optical sensing area; and forming an aperture in the thick metal layer, wherein the aperture aligning with the optical sensing area.

Abstract: An optical sensor includes a semiconductive layer having an electrical circuit area and an optical sensing area, a sample-holding portion over the optical sensing area, a light-guiding structure between the sample-holding portion and the optical sensing area, and an electrical interconnect structure over the electrical circuit area. The electrical interconnect structure is integrally formed with the light-guiding structure, and the light-guiding structure is configured to direct an emitting light from the sample-holding portion to the optical sensing area.

Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relatively small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed. A number of shallow trenches are formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask has an opening at a central part of each relatively large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed. The oxide layer is planarized to expose the silicon nitride layer.

Abstract: A method of forming a partial reverse active mask. A mask pattern comprising a large active region pattern with an original dimension and a small active region pattern is provided. The large active region pattern and the small active region pattern are shrunk until the small active region pattern disappears. The large active region pattern enlarged to a dimension slightly smaller than the original dimension.

Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relatively small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed. A number of shallow trenches are formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask has an opening at a central part of each relatively large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed. The oxide layer is planarized to expose the silicon nitride layer.

Abstract: A fabrication method for an integrated device having a capacitor in an interconnect system is described. At least a first exposed metal line and a second metal line are provided in an insulating layer. A stack layer is deposited and patterned to form a film stack structure over the second metal line. An inter-metal dielectric layer is formed over the film stack structure, the first metal line and the insulating layer. At least a first dual damascene interconnect and a second dual damascene interconnect are formed over and in contact with the first metal line and the film stack structure, respectively.

Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relative large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed A number of shallow trenches are formed between the active regions An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial rever active mask has an opening at a central part of each relative large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed The oxide layer is planarized to expose the silicon nitride layer.

Abstract: A method of designing an active region pattern with a shifted dummy pattern, wherein an integrated circuit having an original active region pattern thereon is provided. The original active region pattern is expanded with a first parameter of line width to obtain a first pattern. By subtracting the first pattern, a second pattern is obtained. A dummy pattern which comprises an array of a plurality of elements is provided. By shifting the elements, a shifted dummy pattern is obtained. The second pattern and the shifted dummy pattern are combined, so that an overlapped region thereof is extracted as a combined dummy pattern. The combined dummy pattern is expanded with a second parameter of line width, so that a resultant dummy pattern is obtained. The resultant dummy pattern is added to the first pattern, so that the active region pattern with a shifted dummy pattern is obtained.

Abstract: A fabrication method for an integrated device having a capacitor in an interconnect system is described. At least a first exposed metal line and a second metal line are provided in an insulating layer. A stack layer is deposited and patterned to form a film stack structure over the second metal line. An inter-metal dielectric layer is formed over the film stack structure, the first metal line and the insulating layer. At least a first dual damascene interconnect and a second dual damascene interconnect are formed over and in contact with the first metal line and the film stack structure, respectively.

Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relative large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed A number of shallow trenches are formed between the active regions An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial rever active mask has an opening at a central part of each relative large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed The oxide layer is planarized to expose the silicon nitride layer.

Abstract: A method of designing an active region pattern with a shifted dummy pattern, wherein an integrated circuit having an original active region pattern thereon is provided. The original active region pattern is expanded with a first parameter of line width to obtain a first pattern. By subtracting the first pattern, a second pattern is obtained. A dummy pattern which comprises an array of a plurality of elements is provided. By shifting the elements, a shifted dummy pattern is obtained. The second pattern and the shifted dummy pattern are combined, so that an overlapped region thereof is extracted as a combined dummy pattern. The combined dummy pattern is expanded with a second parameter of line width, so that a resultant dummy pattern is obtained. The resultant dummy pattern is added to the first pattern, so that the active region pattern with a shifted dummy pattern is obtained.

Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relative large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed. A number of shallow trenches are formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial rever active mask has an opening at a central part of each relative large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed. The oxide layer is planarized to expose the silicon nitride layer.

Abstract: A method for fabricating a semiconductor device. A shallow trench isolation is formed by forming a well region, a gate oxide layer and a wiring layer prior to forming a trench in the substrate. The trench is then filled with silicon oxide layer doped with germanium, nitrogen, titanium or other refractory metal. In addition, a MOS device is also fabricated with a gate buried in the substrate with a shallow trench isolation filled with the doped silicon oxide layer formed therein.

Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relative large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed. A number of shallow trenches are formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial rever active mask has an opening at a central part of each relative large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed. The oxide layer is planarized to expose the silicon nitride layer.

Abstract: A method of forming a partial reverse active mask. A mask pattern comprising a large active region pattern with an original dimension and a small active region pattern is provided. The large active region pattern and the small active region pattern are shrunk until the small active region pattern disappears. The large active region pattern enlarged to a dimension slightly smaller than the original dimension.

Abstract: A method for manufacturing a MOS transistor. The method includes the steps of providing a substrate having a gate electrode thereon, and then depositing a first dielectric material over the gate electrode and the substrate to form a conformal first dielectric layer. Next, spacers are formed over the first dielectric on the sidewalls of the gate electrode. Thereafter, a portion of the first dielectric layer is removed by performing an isotropic etching operation. Ultimately, a portion of the first dielectric layer between the spacers and the gate electrode as well as between the spacers and the substrate are removed. Finally, a second dielectric material is deposited over the gate electrode forming voids in the space between the gate electrode and the spacer as well as between the substrate and the spacer.

Abstract: A method for preventing boron segregation and out diffusion to form PMOS devices is disclosed. The method includes providing a semiconductor substrates and the formation of a gate oxider layer as well as a gate layer on top of the semiconductor substrate. Next, a photoresist layer is formed on a top surface of the gate layer, moreover, a pattern is transferred onto the photoresist layer after being put through an exposure and a development. Furthermore, the gate layer and the oxide layer are then etched using the photoresist layer as a mask, and the photoresist layer is removed afterward. In succession, a thin silicon nitride layer is grown utilizing RTCVD processing. Thereafter, high doped drain regions of boron ion shallow junctions are formed by carrying out ion implantation. A silicon oxide layer is deposited using LPCVD, and forming spacers by etching the silicon oxide layer. Next, a heavy doping of boron ions proceeds, as well as an annealing process.

Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relative large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed. A number of shallow trenches are formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial rever active mask has an opening at a central part of each relative large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed. The oxide layer is planarized to expose the silicon nitride layer.

Abstract: A method of forming a partial reverse active mask. A mask pattern comprising a large active region pattern with an original dimension and a small active region pattern is provided. The large active region pattern and the small active region pattern are shrunk until the small active region pattern disappears. The large active region pattern enlarged to a dimension slightly smaller than the original dimension.