Abstract: A method for fabrication a shallow trench isolation (STI) structure by combining uses of a STI process and a local oxidation (LOCAS) process is provided. The method includes forming a first liner oxide layer over a substrate, on which a patterned hard material layer is formed. A hard spacer is formed on each sidewall of the hard material layer. A LOCOS structure is formed on the substrate other than the hard spacer and the hard material layer. Then, the hard spacer is removed to expose a portion of the pad oxide on the substrate. A trench is formed in the substrate on each side of the LOCOS structure. A conformal second liner oxide layer is formed on the inner surface of the trench. The trench is filled with a polysilicon layer, having a surface higher than the substrate surface. A second thermal process is performed to oxidize the polysilicon layer so as to merge the LOCOS structure to cover the surface of the polysilicon layer.

Abstract: A method for fabricating a semiconductor device. A shallow trench isolation is formed by forming a well region, a gate oxide layer and a wiring layer prior to forming a trench in the substrate. The trench is then filled with silicon oxide layer doped with germanium, nitrogen, titanium or other refractory metal. In addition, a MOS device is also fabricated with a gate buried in the substrate with a shallow trench isolation filled with the doped silicon oxide layer formed therein.

Abstract: A method for fabricating, a shallow trench isolation structure. A pad oxide layer and a silicon nitride layer are formed in sequence on a substrate. A trench is formed in the substrate and a liner oxide layer is formed on a sidewall of the trench. A doped silicon dioxide layer is formed on the silicon nitride layer and fills the trench. An annealing process is performed to density the doped silicon dioxide layer. A portion of the doped silicon dioxide layer is removed to expose the silicon nitride layer by a planarization process.

Abstract: A method of trench polishing. A semiconductor substrate is provided. A photo-mask with a pattern is provided. The method of fabricating the photo-mask further comprising providing an original pattern which comprises a plurality of active regions with individual size. The original pattern is enlarged outwards to connect and merge some of the active regions. The active regions is diminished inwards until some small active regions eliminate, the diminished line width being denoted as B. A reverse treatment is performed to obtain a reverse pattern. The reverse pattern is enlarged with a line width C. The reverse pattern is combined with the original pattern. The substrate is patterned with the photo-mask with the combined pattern. An insulation layer is formed on the substrate. The insulation layer is polished.

Abstract: A method for forming a MOS transistor is provided. A gate oxide layer, a polysilicon layer, a barrier layer and a conductive layer are sequentially formed on a provided substrate. A photolithography and etching process is carried out to remove a portion of the conductive layer and a portion of the barrier layer until exposing the polysilicon layer. An ion implantation is performed to form lightly doped regions in the substrate using the remaining conductive layer and the remaining barrier layer as a mask. A spacer is formed on the side-wall of the conductive layer and on the side-wall of the barrier layer. The polysilicon layer and the gate oxide layer, which are in positions other than those of the remaining conductive layer and the spacer, are removed. The remaining conductive layer and the remaining polysilicon layer constitute a gate with an inversed, T-shaped cross-section.

Abstract: A method for manufacturing metal oxide semiconductor field effect transistor is disclosed. The metal oxide semiconductor field effect transistor is formed by a specific fabricating process that disadvantages of thermal damage are effectively prevented. According to the method, first a substrate is provided. Second, an isolation and a well are formed in the substrate, and then a first dielectric layer, a conductive layer and an anti-reflection coating layer are formed on the substrate sequentially. Third, a gate is formed on the substrate, and then a source and a drain are formed in the substrate and a spacer is formed on the substrate. Fourth, both source and drain are annealed, and then a first salicide is formed on both source and drain. Fifth, a second dielectric layer is formed on the substrate and is planarized, where the anti-reflecting coating layer is totally removed and the conductive layer is partially removed. Sixth, a second salicide is formed on the conductive layer.

Abstract: A method for fabricating a mask comprises a first pattern in respective of active areas, and a second pattern in respective of dummy active areas. After removing the first pattern, the profiles of the dummy active areas are enlarged. The N-well boundary and the P-well boundary of the second pattern is respectively shielded to form a first composed pattern and a second composed pattern comprising the larger dummy active areas and a shielding pattern. The dummy active areas on the substrate are shielded by the patterns of the embodiment during the process of ion implantation. Thus the resistivity of the dummy active areas is increased, whereby the parasitic capacitance can be prevented from being too large and affecting the performance of the devices.

Abstract: A fabrication equipment to form an opening plug is provided. The equipment at least includes a load/unload chamber, a degas chamber, an usual sputtering chamber, a radio frequency (RF) sputtering chamber, a physical vapor deposition (PVD) chamber, and a chemical vapor deposition (CVD). The load/unload chamber is used to load a substrate. The degas chamber is used to remove moisture on the substrate. The usual sputtering chamber is used to form an opening on the substrate. The PVD chamber is used to form a first glue layer. The RF sputtering chamber is used to remove an overhang structure on the first glue layer. The CVD chamber is used to form a second glue layer over the first glue layer.

Abstract: A method for preventing boron segregation and out diffusion to form PMOS devices is disclosed. The method includes a semiconductor substrate which is provided and forms a gate oxide layer as well as a gate layer on top of the semiconductor substrate. Next, a photoresist layer is formed on a top surface of the gate layer, moreover, pattern transfers onto the photoresist layer after going through an exposure and a development. Furthermore, the gate layer and the gate oxide layer are then etched by using the photoresist layer as a mask, and the photoresist layer is removed afterward. In succession, a thin nitride oxide (NO, N2O) layer is grown by utilizing rapid thermal oxidation (RTO) and rapid thermal nitridation (RTN). Hereafter, high doped drain regions of boron ion shallow junctions are formed by carrying out ion implantation. A TEOS layer and a silicon nitride layer are deposited by using LPCVD, and forming spacers by etching the silicon nitride layer and the TEOS layer.

Abstract: A method for manufacturing semiconductor device. The method includes the steps of providing a substrate that has a gate structure thereon, and then forming offset spacers on the sidewalls of the gate structure. Thereafter, a thin oxide annealing operation is conducted, and then a first ion implantation is carried out using the gate structure and the offset spacers as a mask to form lightly doped drain regions in the substrate. Subsequently, secondary spacers are formed on the exterior sidewalls of the offset spacers. Finally, a second ion implantation is carried out using the gate structure, the offset spacers and the secondary spacers as a mask to form source/drain regions within the lightly doped drain regions.

Abstract: A method of designing an active region pattern with a shifted dummy pattern, wherein an integrated circuit having an original active region pattern thereon is provided. The original active region pattern is expanded with a first parameter of line width to obtain a first pattern. By subtracting the first pattern, a second pattern is obtained. A dummy pattern which comprises an array of a plurality of elements is provided. By shifting the elements, a shifted dummy pattern is obtained. The second pattern and the shifted dummy pattern are combined, so that an overlapped region thereof is extracted as a combined dummy pattern. The combined dummy pattern is expanded with a second parameter of line width, so that a resultant dummy pattern is obtained. The resultant dummy pattern is added to the first pattern, so that the active region pattern with a shifted dummy pattern is obtained.

Abstract: A method is described for manufacturing a shallow trench isolation. The method comprises the steps of providing a substrate having a pad oxide layer, a mask layer and a trench, wherein the trench penetrates through the mask layer and the pad oxide layer and into the substrate. A liner oxide layer is formed on a portion of the sidewall of the trench in the substrate. A silicon layer is formed in the trench with a same surface level as the interface between the substrate and the pad oxide layer and an insulating layer is formed on the silicon layer.

Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor is provided. The method has steps of sequentially forming an oxide layer, a polysilicon layer and a cap layer on a semiconductor substrate to form a first-stage gate. An interchangeable source/drain region with a lightly doped drain (LDD) structure is formed in the substrate at each side of the first-stage gate. An insulating layer is formed over the substrate, and is planarized so as to exposed the cap layer. Removing the exposed cap layer forms an opening that exposes the polysilicon layer. Using the insulating layer as a mask, a self-aligned selective local implantation process is performed to form a threshold-voltage doped region and an anti-punch-through doped region below the oxide layer in the substrate. A conductive layer is formed over the substrate to fill the opening.

Abstract: A method of fabricating a metal oxide semiconductor includes formation of a gate on a substrate. A source/drain extension is formed beside the gate in the substrate. An ion implantation step is performed to implant heavy impurities with a low diffusion coefficient in the substrate. A heavily doped halo region is formed in the substrate below the source/drain extension. A tilt-angled halo implantation step is performed to form a halo-implanted region in the substrate to the side of the source/drain extension below the gate.

Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relative large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed. A number of shallow trenches are formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial rever active mask has an opening at a central part of each relative large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed. The oxide layer is planarized to expose the silicon nitride layer.

Abstract: A method of fabricating a glue layer of a contact/via. A substrate is provided and a contact/via opening is formed within a dielectric layer on the substrate to expose the substrate. A glue layer is formed to cover the contact/via opening and conformal the structure. An RF sputtering process is performed on the substrate to remove an overhang structure on the upper corner of the glue layer while it is formed. A conductive layer is then formed in the contact/via opening to electrically connect to the substrate.

Abstract: A method for forming a shallow trench isolation (STI) structure adds an etching back process to a conventional method which only uses a chemical mechanical process (CMP) process to accomplish the STI structure. In the method of the invention, the CMP process preliminarily planarizes a substrate to remove an insulation layer above the trench and uses the etching back process to accomplish the STI structure.

Abstract: A method for fabricating an embedded DRAM. A substrate having a memory circuit region and a logic circuit region is provided. A first gate, a first source/drain region and a second source/drain region are formed in the memory circuit region. A second gate and a third source/drain region are formed in the logic circuit region. A first dielectric layer is formed over the substrate. In the first dielectric layer, a first contact hole is formed to expose the first source/drain region and a second contact hole is formed to expose the second gate and the third source/drain region. A bit line is formed to electrically couple with the first source/drain region through the first contact hole. A local interconnect is formed to electrically couple with the second gate and the third source/drain region through the second contact hole. A second dielectric layer is formed over the substrate.

Abstract: A method of manufacturing MOS device including the steps of providing a semiconductor substrate that has a device isolation structure thereon, and then depositing a gate oxide layer, a polysilicon layer and an anti-reflection coating in sequence over the substrate. Next, a gate structure is patterned out of the gate oxide layer, the polysilicon layer and the anti-reflection coating. Then, spacers are formed on the sidewalls of the gate structure. Thereafter, a metal silicide layer is formed over source/drain regions. After that, an inter-layer dielectric (ILD) layer is formed over the gate structure and the entire substrate. Then, the inter-layer dielectric layer is planarized to expose the anti-reflection coating. Next, the anti-reflection coating is removed, and then a barrier layer is deposited over the inter-layer dielectric layer and the polysilicon layer. Subsequently, a conductive layer is deposited over the barrier layer.

Abstract: A method for fabricating a local interconnect. A gate having a gate oxide layer, a gate polysilicon layer and a cap layer is formed on a provided substrate. A spacer is formed on the sidewall of the gate, and a source/drain region is formed in the substrate. A planarized dielectric layer is formed over the substrate to expose the cap layer. A portion of the dielectric layer and the spacer on one side of the gate is removed to form an opening, so that the source/drain region is exposed. The opening is transformed into a local-interconnect opening by removing the cap layer. A local interconnect is formed by forming a conductive layer in the local-interconnect opening.