Abstract: The multiaxial inertial sensor of movements is a micro/nano sensor that makes it possible to couple at least one accelerometer with other structures, either accelerometers or gyroscopes, by an oscillating disk structure. The oscillating disk also forms an inertial sensor such as a gyrometer. This single-chip structure associating both gyroscopes and accelerometers makes it possible to achieve detections and measurements in up to 6 axes, in other words 3 accelerometer axes and 3 gyroscope axes, and to exert control by a single and unique electronic unit, thus permitting a single automatic control loop in excitation and a single electronic reading chip. Application to technologies known as MEMS.

Abstract: An electrical stimulation system including: a mechanism generating at least one electrical signal to be applied to a biological tissue that is to stimulated and measuring a response of the biological tissue to each electrical signal; a calculation mechanism estimating, based on each electrical signal and on a corresponding response of the biological tissue, at least one parameter of an electrical model of the biological tissue and its interface with the electrical stimulation system and determining, using the model, at least one parameter of a stimulation pulse to be applied to the biological tissue by the electrical stimulation system; and a mechanism generating a stimulation pulse to be applied to the biological tissue.

Abstract: The present invention relates to a method for chemically treating the surface condition of a silicon substrate for the roughness contrast characterized in that it comprises at least two successive treatment cycles, with each treatment cycle comprising a first step including placing in contact the silicon substrate with a first solution containing water diluted hydrofluoric (HF) acid and then a second step carried out at a temperature of less than 40° C., comprising placing in contact the silicon layer with a second solution containing water (H2O) diluted ammonium hydroxide (NH4OH) and hydrogen peroxide (H2O2), in order to obtain a roughness of less than 0.100 nanometer on a 1 ?m×1 ?m area upon completion of the treatment cycles. The invention will be applied in the field of microelectronics for the production of transistors, of surfaces for photovoltaic panels or for direct molecular bonding.

Abstract: The present invention relates to a method for manufacturing a film of Cu2ZnSnS4 (CZTS) on a metal or metal oxide substrate by successive ion layer adsorption and reaction (SILAR), characterized by the fact that it comprises at least two cycles, each cycle comprising the following successive steps: immersion of the substrate in a cationic solution comprising copper sulfate (CuSO4), tin sulfate (SnSO4) and zinc sulfate (ZnSO4), referred to as the precursors; rinsing by immersion of the substrate in deionized water; immersion of the substrate in an anionic solution comprising sodium sulfide (Na2S); rinsing by immersion of the substrate in deionized water; the concentration ratio of the copper (Cu2+), zinc (Zn2+) and tin (Sn2+) cations and of the sulfur (S2?) anion is 1:1:1:1 or 1:0.5:0.5:1. The invention will be applicable more particularly in the photovoltaic field, especially for production of thin-film, especially nanostructured photovoltaic cells, such as the ETA (Extremely Thin Absorber) cell.

Abstract: Digital loudspeaker comprising a support, a plurality of first membranes suspended on the support, said first membranes being bistable, and said loudspeaker comprising actuator for each of the first membranes that can change each of the first membranes from a first stable state to a second stable state and vice versa, and a controller for controlling said first actuator.

Abstract: A method for forming gate, source, and drain contacts on a MOS transistor having an insulated gate including polysilicon covered with a metal gate silicide, this gate being surrounded with at least one spacer made of a first insulating material, the method including the steps of a) covering the structure with a second insulating material and leveling the second insulating material to reach the gate silicide; b) oxidizing the gate so that the gate silicide buries and covers the a silicon oxide; c) selectively removing the second insulating material; and d) covering the structure with a first conductive material and leveling the first conductive material all the way to a lower level at the top of the spacer.

Abstract: A method of determining an applicable threshold for determining the critical dimension of a category of patterns imaged by atomic force scanning electron microscopy is presented. The method includes acquiring, from a plurality of patterns, a pair of images for each pattern; for each pair of images determining a reference critical dimension via an image obtained by a reference instrumentation and determining an empirical threshold applicable to an image obtained by a CD-SEM instrumentation such that the empirical threshold substantially corresponds to the reference critical dimension; determining a threshold applicable to a category of patterns, the threshold being determined from a plurality of empirical thresholds.

Abstract: A microelectronic wireless transmission device including: a substrate able to be traversed by radio waves intended to be emitted by the device, an antenna, an electrical power supply, an integrated circuit, electrically connected to the antenna and to the electrical power supply, and able to transmit to the antenna electrical signals intended to be emitted by the antenna in the form of the said radio waves, a cap rigidly connected to the substrate and forming, with the substrate, at least one cavity in which the antenna and the integrated circuit are positioned, where the cap comprises an electrically conductive material connected electrically to an electrical potential of the electrical power supply and/or of the integrated circuit, and able to form a reflector with regard to the radio waves intended to be emitted by the antenna.

Abstract: The present invention relates to a reactor for atomic layer deposition (ALD), comprising a reaction chamber comprising a platen and bounded internally by surfaces; at least one inlet orifice and at least one outlet orifice, each emerging from one of the surfaces bounding the chamber. The reactor furthermore comprises, within it, at least one wall apertured with at least one orifice, the apertured wall extending around the platen and over at least most of the height between the lower surface and the upper surface, at least one orifice in at least one of the apertured walls not facing the inlet orifice so as to form chicanes in the flow of gaseous precursor from each inlet orifice to the platen.

Abstract: A method for estimating molecular parameters in a sample comprising the following steps: passing the sample through a processing chain including a chromatography step; thereby obtaining a representative signal of molecular parameters as a function of at least one variable of the processing chain; and estimating the molecular parameters using a signal processing device by inverting a direct analytical model of said signal defined as a function of the molecular parameters and technical parameters of the processing chain. Moreover, the processing chain includes a step for multiple measurements of the same product from the chromatography step, the direct analytical model of said signal comprises modelling of this multiple measurement step, and this modelling requires at least one common characteristic of the signals obtained from these multiple measurements.

Abstract: An assembly comprising a sample and a device for generating a high temperature gradient in said sample, comprises: a chamber inside which said sample is placed; a resistor passing through said sample; first induction means at the periphery of the chamber to create an electromagnetic field; second induction means connected to said resistor and capable of picking up said electromagnetic field so as to create an induced current circulating in said resistor.

Abstract: A first light source has a first wavelength corresponding to an excitation wavelength of a fluorophore. The excitation wavelength and an emission wavelength of the fluorophore delineate a predetermined interval. A second light source has a second wavelength offset with respect to the first wavelength so as to be outside said predetermined interval. The offset between the first and second wavelengths is comprised between 30 nm and 100 nm. A camera comprises a filter opaque to the first and second wavelengths and transparent to the emission wavelength and to wavelengths substantially higher than the higher of the first and second wavelengths. The light sources and camera are synchronized to alternately activate one of the light sources and make the camera alternately acquire a fluorescence image and a background noise image.

Abstract: A process for manufacturing a stacked structure comprising at least one thin layer bonded to a target substrate, in which a thin layer is formed by introduction gaseous species into an initial substrate, to form a weakened layer separating a film from the rest of the initial substrate, a first contact face of the thin layer is bonded to a face of an intermediate substrate by molecular adhesion, and the initial substrate is fractured at the weakened layer so as to expose a free face of the thin layer. The intermediate substrate is then removed in order to obtain the stacked structure.

Abstract: A method for measuring the changes of the electrical performance of an FDSOI transistor between a first and a second state of the transistor after an operating period t1, including the following steps: measurement of the transistor's capacities C1 and C2 respectively in the first and second states, according to a voltage VFG applied between the gate and the source and drain areas, determination, in relation to characteristic C1(VFG) varying between a maximum value Cmax and a minimum value Cmin, with three inflection points, of an ordinate value Cplat of C1(VFG) at the second inflection point of C1(VFG), and of two abscissa values VUpper(0) and VLower(0) of C1(VFG) according to equations VUpper(0)=C1?1((Cmax+Cplat)/2) and VLower(0)=C1?1((Cmin+Cplat)/2), determination, from characteristic C2(VFG), of two abscissa values VUpper(t1) and VLower(t1) of C2(VFG) according to equations VUpper(t1)=C2?1((Cmax+Cplat)/2) and VLower(t1)=C2?1((Cmin+Cplat)/2), determination of variations of defect densities ?Dit1, ?Dit2 b

Abstract: Microelectronic substrate comprising at least: a support layer, a top layer comprising at least one semiconductor, a layer comprising at least one organic material able to be etched selectively with respect to the semiconductor of the top layer by using a dry etching, and disposed between the support layer and the top layer, and also comprising one or more portions of dielectric material the hardness of which is greater than that of the organic material, disposed in the layer of organic material, and the thickness of which is substantially equal to that of the layer of organic material.

Abstract: The present invention relates to an inertial micro-sensor of angular displacements comprising at least one inertial mass (112, 1210) movable in space (x, y, z); an exciter (131) configured to generate a first vibratory movement of the inertial mass along a first direction (X) included in the plane (x, y), so as to generate a first Coriolis force induced by an angular displacement of the inertial mass (112, 1210) around a second direction (Y) included in the plane (x, y) and perpendicular to the first direction (X); an exciter (131) configured to generate a second vibratory movement of the inertial mass along the second direction (Y), so as to generate a second Coriolis force induced by an angular displacement of the inertial mass (112, 1210) around the first direction (X), and means for detecting the first Coriolis force and the second Coriolis force, characterized by the fact that the detection means comprise a common detector for the first Coriolis force and the second Coriolis force and configured to produ

Abstract: The invention concerns a method for managing a network of a plurality of small cell base stations arranged in a macro-cell and linked to a base station of the macro-cell, each small cell base station being adapted to cover a small cell of the macro-cell and to be linked via radio to at least one mobile terminal present in the small cell.

Abstract: The invention relates to a method for managing a network of a plurality of base stations of small cells, placed in a region of a macrocell in which at least one terminal is found, each small cell base station being adapted for covering a small cell, the method being characterized in that: a set A of at least one small cell covering said at least one terminal present in the region, is determined; the smallest subset B of at least one small cell allowing coverage of said at least one terminal is selected from said set A; only said at least one small cell of the subset B will have to be active.

Abstract: A method for stressing a pattern having a pattern surface, in a layer of semiconductive material that can be silicon on the surface of a stack of layers generated on the surface of a substrate, said stack comprising at least one stress layer of alloy SixGey with x and y being molar fractions, and a buried layer of silicon oxide, comprises: etching at the periphery of a surface of dimensions greater than said pattern surface, of the buried layer of silicon oxide and layer of alloy SixGey over a part of the depth of said layer of alloy; the buried layer of silicon oxide being situated between said layer of semiconductive material and said stress layer of alloy SixGey. In a transistor structure, etching at the periphery of said surface obtains a pattern thus defined having dimensions greater than the area of interest situated under the gate of the transistor.

Abstract: A method for manufacturing an integrated circuit, including the steps of forming first transistors on a first semiconductor layer; depositing a first insulating layer above the first semiconductor layer and the first transistors, and leveling the first insulating layer; depositing a conductive layer above the first insulating layer, and covering the conductive layer with a second insulating layer; bonding a semiconductor wafer to the second insulating layer; thinning the semiconductor wafer to obtain a second semiconductor layer; and forming second transistors on the second semiconductor layer.