Abstract: A display substrate includes a main display area, a secondary display area and a transition area; the secondary display area includes an aperture region, a first peripheral region and a second peripheral region, at least part of the first peripheral region being located between the aperture region and the second peripheral region; the aperture region includes display sub-pixels; the first peripheral region includes display sub-pixels and first virtual sub-pixels; the second peripheral region includes display sub-pixels and second virtual sub-pixels; the density of the display sub-pixels of the aperture region, the density of the display sub-pixels of the first peripheral region and the density of the display sub-pixels of the second peripheral region are the same; at least part of the transition area is located between the main display area and the second peripheral region; the main display area and the transition area both includes display sub-pixels.

Abstract: A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit and an output circuit; the driving signal generation circuit generates and outputs the Nth stage of driving signal; the gating circuit controls to write the gating input signal into the first node; the output control circuit performs a NAND operation on the Nth stage of driving signal and the potential of the second terminal of the output control circuit to obtain a first output signal; the output circuit inverts the first output signal to obtain and provide an output driving signal through the output driving terminal; N is a positive integer.

Abstract: A pixel driving circuit includes: a driving circuit, connecting a first node, a second node, and a third node, and configured to provide a driving current to the third node by using the second node; a compensation circuit, connecting the third node, a fourth node, and a first gate driving signal end, and configured to conduct the third node and the fourth node; a first reset circuit, connecting a first initial signal end, a fifth node, and a first reset signal end, and configured to transmit a signal of the first initial signal end to the fifth node; a first isolation circuit, connecting the first node and the fourth node, and configured to conduct the first node and the fourth node; and a second isolation circuit, connecting the first node and the fifth node, and configured to conduct the first node and the fifth node.

Abstract: A data search apparatus includes a logical search circuit and a memory, and the logical search circuit is connected to the memory through a databus. The databus can access all memory resources, and each part of databus resource can access all the memory resources. A logical search resource provided by the logical search circuit can be divided into a plurality of parts as required, and each part of logical resource can access node data in the memory through the bus resource.

Abstract: A sample refrigeration storage device and a sample flow-line analysis system are provided. The sample refrigeration storage device includes: a refrigeration storage area including a storage area frame, a refrigeration placement rack and a first refrigeration mechanism; a refrigeration operation area including an operation area frame, a sample sorting mechanism, a sample rack-loading mechanism and a second refrigeration mechanism, the operation area frame being in communication with the storage area frame to form a closed cavity, and the sample sorting mechanism and the sample rack-loading mechanism cooperating to offload samples from the refrigeration placement rack through an access opening, and to load samples onto the refrigeration placement rack through the access opening; a sample transport track; and a central control system.

Abstract: A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit, an output circuit, a voltage control circuit and a second node control circuit; the driving signal generation circuit generates an Nth stage of driving signal; the output control circuit controls to connect the first control node and the second node under the control of the potential of the first node; the gating circuit writes a gating input signal into the first node under the control of a gating control signal; the voltage control circuit controls a potential of the second node according to the potential of the first node; the second node control circuit controls to connect the second node and the first voltage terminal under the control of the potential of the first node.

Abstract: A conveying track includes a frame, a delivery track is arranged on the frame, and is formed by assembling one or more kinds of H-shaped tracks, T-shaped tracks, L-shaped tracks, U-shaped tracks and I-shaped tracks, and a sample blocking device and/or a diversion device are/is arranged on the delivery track. The conveying track of the present invention has a more flexible track layout, and satisfies the diversified layout requirements of a laboratory delivery system, and thus the installation efficiency of the track is improved.

Abstract: A display panel and a display device are provided. The display panel includes: a plurality of first pixel units, a plurality of second pixel units, a plurality of third pixel units and a plurality of first data lines. An effective light-emitting area of the first pixel unit is larger than an effective light-emitting area of the second pixel unit, and larger than an effective light-emitting area of the third pixel unit; an orthographic projection of the first data line on the base substrate is not overlapped with an orthographic projection of any one of the first electrode of the first pixel unit, the first electrode of the second pixel unit, and the first electrode of the third pixel unit on the base substrate.

Abstract: Disclosed is a display panel, including: a base substrate including a first display region, a second display region, and a routing region; a first anode layer, a first light-emitting layer and a first cathode layer disposed in the first display region and sequentially stacked in a direction going away from the base substrate; a second cathode layer, a second anode layer, a second light-emitting layer, and a third cathode layer disposed in the second display area and sequentially stacked in the direction going away from the base substrate, and a first signal transmission layer disposed in the routing region; wherein the first signal transmission layer is connected to the second cathode layer and the first cathode layer, and the first signal transmission layer is further configured to receive a power supply signal.

Abstract: A pixel circuit and a driving method thereof, a display panel, and display device are disclosed. The pixel circuit includes a data writing circuit, a driving circuit, and a compensation circuit. The compensation circuit is connected to a control terminal, a first terminal, and a second terminal of the driving circuit, and is configured to write a compensation voltage based on a first reset voltage into the control terminal of the driving circuit; the data writing circuit is connected to the control terminal of the driving circuit and is configured to write a coupling voltage based on a data voltage into the control terminal of the driving circuit; and the driving circuit is configured to control a driving current for driving a light-emitting element to emit light under control of a voltage applied to the control terminal of the driving circuit.

Abstract: The present disclosure provides a driving circuitry, a driving method, a driving module, and a display device. The driving circuitry includes a driving signal generation circuitry, a gating circuitry, an output control circuitry and an output circuitry. The driving signal generation circuitry is configured to perform a shifting operation on an (N?1)th-level driving signal to obtain an Nth-level driving signal. The gating circuitry is configured to write a gating input signal into a first node under the control of a gating control signal. The output control circuitry is configured to perform an NAND operation on the Nth-level driving signal and a potential at a second end of the output control circuitry to obtain a first output signal. The output circuitry is configured to perform phase inversion on the first output signal to obtain and provide an output driving signal through an output driving end, where N is a positive integer.

Abstract: Provided are a display substrate and a display device. The display substrate includes a base substrate, and a driving circuit layer and a light-emitting device layer on the base substrate. The display substrate includes a light-transmitting display area and a normal display area, the normal display area surrounds at least a portion of the light-transmitting display area. The normal display area includes multiple normal driving circuits and multiple dummy driving circuits; some dummy driving circuit are used for driving light-emitting devices located in the light-transmitting display area. The display substrate further includes multiple normal data lines coupled to the normal driving circuits; at least one normal data line is coupled to a data signal input terminal through a data lead; an orthographic projection of the data lead onto the base substrate at least partially overlaps an orthographic projection of the dummy driving circuit onto the base substrate.

Abstract: A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit, an output circuit, a voltage control circuit and a second node control circuit; the driving signal generation circuit generates an Nth stage of driving signal; the output control circuit controls to connect the first control node and the second node under the control of the potential of the first node; the gating circuit writes a gating input signal into the first node under the control of a gating control signal; the voltage control circuit controls a potential of the second node according to the potential of the first node; the second node control circuit controls to connect the second node and the first voltage terminal under the control of the potential of the first node.

Abstract: A catalyst for selective hexane and/or butene formation from ethylene. The catalyst is formed by grafting Cr or Mn to an inorganic support. The grafted metal site is reduced, forming a catalyst that is selective for selective trimerization of ethylene to hexene and/or butene.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes: a base substrate, and a compensation signal line and a plurality of sub-pixels on the base substrate. The sub-pixel includes a sub-pixel driving circuit. The sub-pixel driving circuit includes a driving transistor and a compensation structure. The compensation structure is coupled to the corresponding compensation signal line. An orthographic projection of the compensation structure onto the base substrate is located at a side of an orthographic projection of a gate electrode of the driving transistor onto the base substrate.

Abstract: In a pixel circuit, a data writing-in circuit is configured to control to connect the data line and the second end of the driving circuit under the control of a first scan signal provided by the first scan line; a reset circuit is configured to control to connect the reset voltage line and the second end of the driving circuit under the control of a third scan signal provided by the third scan line; or control to connect the reset voltage line and the first end of the driving circuit under the control of the third scan signal; a driving circuit is configured to control to connect the first end of the driving circuit and the second end of the driving circuit under the control of a potential of a control end of the driving circuit.

Abstract: A display substrate is provided. The display substrate includes a base substrate and a plurality of reset signal lines. The base substrate includes a display region, the display region includes a plurality of sub-pixels arranged in array, each of the plurality of sub-pixels includes a pixel driving circuit and a light-emitting element. The plurality of reset signal lines extend in a first direction, the plurality of reset signal lines include a plurality of first reset signal lines for providing a first reset signal and a plurality of second reset signal lines for providing a second reset signal, and one of the plurality of first reset signal lines and one of the plurality of second reset signal lines are respectively connected to pixel driving circuits of a plurality of sub-pixels located in a same row.

Abstract: Disclosed are a display panel and a display device. The pixel circuit in the display panel includes a control circuit, a drive circuit, and a regulating circuit. The control circuit controls the potential of the coupled control node based on the gate drive signal provided by the gate line and the data signal provided by the data line. The drive circuit drives the light-emitting element to emit light based on the potential of the control node and the drive power signal provided by the drive power line. The regulating circuit adjusts the potential of the control node through the coupling effect based on the drive power signal and the initial power signal provided by the initial power line.

Abstract: A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit and an output circuit; the driving signal generation circuit generates and outputs the Nth stage of driving signal; the gating circuit controls to write the gating input signal into the first node; the output control circuit performs a NAND operation on the Nth stage of driving signal and the potential of the second terminal of the output control circuit to obtain a first output signal; the output circuit inverts the first output signal to obtain and provide an output driving signal through the output driving terminal; N is a positive integer.

Abstract: A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit, an output circuit and a voltage control circuit; the driving signal generation circuit generates an Nth stage of driving signal, the output control circuit connects the first control node and the second node under the control of the potential of the first node; the gating circuit controls to write a gating input signal into the first node under the control of a gating control signal; the voltage control circuit controls a potential of the second node according to a potential of the first node; the output circuit connects the output driving terminal and the first voltage terminal under the control of the potential of the second node, and connects the output driving terminal and the second voltage terminal under the control of the potential of the third control node.