Patents by Inventor Cornelia K. Tsang

Cornelia K. Tsang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10347588
    Abstract: After forming a first electromagnetic radiation blocking layer over a front side of a device wafer, the device wafer is bonded to a handle substrate from the front side. A semiconductor substrate in the device wafer is thinned from its backside. Trenches are formed extending through the device wafer and the first electromagnetic radiation blocking layer such that the device wafer is singulated into semiconductor dies. A second electromagnetic radiation blocking layer portion is formed on a backside surface of and sidewalls surfaces of each of the semiconductor dies such that each of the semiconductor dies are fully encapsulated by the first and second electromagnetic radiation blocking layer portions.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: July 9, 2019
    Assignees: International Business Machines Corporation, JOHNSON & JOHNSON VISION CARE, INC.
    Inventors: Paul S. Andry, Cornelia K. Tsang, Adam Toner
  • Publication number: 20190139938
    Abstract: An electrical device that includes at least two active wafers having at least one through silicon via, and at least one unitary electrical communication and spacer structure present between a set of adjacently stacked active wafers of the at least two active wafers. The unitary electrical communication and spacer structure including an electrically conductive material core providing electrical communication to the at least one through silicon via structure in the set of adjacently stacked active wafers and a substrate material outer layer. The at least one unitary electrical communication and spacer structure being separate from and engaged to the adjacently stacked active wafers, wherein coolant passages are defined between surfaces of the adjacently stacked active wafers and the at least one unitary electrical communication and spacer structure.
    Type: Application
    Filed: January 3, 2019
    Publication date: May 9, 2019
    Inventors: Paul S. Andry, Mark D. Schultz, Cornelia K. Tsang
  • Patent number: 10177116
    Abstract: An electrical device that includes at least two active wafers having at least one through silicon via, and at least one unitary electrical communication and spacer structure present between a set of adjacently stacked active wafers of the at least two active wafers. The unitary electrical communication and spacer structure including an electrically conductive material core providing electrical communication to the at least one through silicon via structure in the set of adjacently stacked active wafers and a substrate material outer layer. The at least one unitary electrical communication and spacer structure being separate from and engaged to the adjacently stacked active wafers, wherein coolant passages are defined between surfaces of the adjacently stacked active wafers and the at least one unitary electrical communication and spacer structure.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: January 8, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul S. Andry, Mark D. Schultz, Cornelia K. Tsang
  • Publication number: 20180342464
    Abstract: After forming a first electromagnetic radiation blocking layer over a front side of a device wafer, the device wafer is bonded to a handle substrate from the front side. A semiconductor substrate in the device wafer is thinned from its backside. Trenches are formed extending through the device wafer and the first electromagnetic radiation blocking layer such that the device wafer is singulated into semiconductor dies. A second electromagnetic radiation blocking layer portion is formed on a backside surface of and sidewalls surfaces of each of the semiconductor dies such that each of the semiconductor dies are fully encapsulated by the first and second electromagnetic radiation blocking layer portions.
    Type: Application
    Filed: July 18, 2018
    Publication date: November 29, 2018
    Inventors: Paul S. Andry, Cornelia K. Tsang, Adam Toner
  • Patent number: 10056337
    Abstract: After forming a first electromagnetic radiation blocking layer over a front side of a device wafer, the device wafer is bonded to a handle substrate from the front side. A semiconductor substrate in the device wafer is thinned from its backside. Trenches are formed extending through the device wafer and the first electromagnetic radiation blocking layer such that the device wafer is singulated into semiconductor dies. A second electromagnetic radiation blocking layer portion is formed on a backside surface of and sidewalls surfaces of each of the semiconductor dies such that each of the semiconductor dies are fully encapsulated by the first and second electromagnetic radiation blocking layer portions.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: August 21, 2018
    Assignees: International Business Machines Corporation, JOHNSON & JOHNSON VISION CARE, INC.
    Inventors: Paul S. Andry, Cornelia K. Tsang, Adam Toner
  • Publication number: 20180211924
    Abstract: After forming a first electromagnetic radiation blocking layer over a front side of a device wafer, the device wafer is bonded to a handle substrate from the front side. A semiconductor substrate in the device wafer is thinned from its backside. Trenches are formed extending through the device wafer and the first electromagnetic radiation blocking layer such that the device wafer is singulated into semiconductor dies. A second electromagnetic radiation blocking layer portion is formed on a backside surface of and sidewalls surfaces of each of the semiconductor dies such that each of the semiconductor dies are fully encapsulated by the first and second electromagnetic radiation blocking layer portions.
    Type: Application
    Filed: January 23, 2017
    Publication date: July 26, 2018
    Inventors: Paul S. Andry, Cornelia K. Tsang, Adam Toner
  • Patent number: 9941250
    Abstract: A package structure to implement two-phase cooling includes a chip stack disposed on a substrate, and a package lid that encloses the chip stack. The chip stack includes a plurality of conjoined chips, a central inlet manifold formed through a central region of the chip stack, and a peripheral outlet manifold. The central input manifold includes inlet nozzles to feed liquid coolant into flow cavities formed between adjacent conjoined chips. The peripheral outlet manifold outputs heated liquid and vapor from the flow cavities. The package lid includes a central coolant supply inlet aligned to the central inlet manifold, and a peripheral liquid-vapor outlet to output heated liquid and vapor that exits from the peripheral outlet manifold. Guiding walls may be included in the flow cavities to guide a flow of liquid and vapor, and the guiding walls can be arranged to form radial flow channels that are feed by different inlet nozzles of the central inlet manifold.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: April 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Thomas J. Brunschwiler, Evan G. Colgan, John U. Knickerbocker, Bruno Michael, Chin Lee Ong, Cornelia K. Tsang
  • Publication number: 20180021774
    Abstract: Techniques for use of wafer bonding techniques for sealing of microfluidic chips are provided. In one aspect, a wafer bonding sealing method includes the steps of: forming a first oxide layer coating surfaces of a first wafer, the first wafer having at least one fluidic chip; forming a second oxide layer on a second wafer; and bonding the first wafer to the second wafer via an oxide-to-oxide bond between the first oxide layer and the second oxide layer to form a bonded wafer pair, wherein the second oxide layer seals the at least one fluidic chip on the first wafer. The second wafer can be at least partially removed after performing the bonding, and fluidic ports may be formed in the second oxide layer. A fluidic chip device is also provided.
    Type: Application
    Filed: October 2, 2017
    Publication date: January 25, 2018
    Inventors: Joshua T. Smith, Cornelia K. Tsang, Chao Wang, Benjamin H. Wunsch
  • Patent number: 9795964
    Abstract: Techniques for use of wafer bonding techniques for sealing of microfluidic chips are provided. In one aspect, a wafer bonding sealing method includes the steps of: forming a first oxide layer coating surfaces of a first wafer, the first wafer having at least one fluidic chip; forming a second oxide layer on a second wafer; and bonding the first wafer to the second wafer via an oxide-to-oxide bond between the first oxide layer and the second oxide layer to form a bonded wafer pair, wherein the second oxide layer seals the at least one fluidic chip on the first wafer. The second wafer can be at least partially removed after performing the bonding, and fluidic ports may be formed in the second oxide layer. A fluidic chip device is also provided.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: October 24, 2017
    Assignee: International Business Machines Corporation
    Inventors: Joshua T. Smith, Cornelia K. Tsang, Chao Wang, Benjamin H. Wunsch
  • Patent number: 9748131
    Abstract: A method for adhesive bonding in microelectronic device processing is provided that includes bonding a handling wafer to a front side of a device wafer with an adhesive comprising phenoxy resin; and thinning the device wafer from the backside of the device wafer while the device wafer is adhesively engaged to the handling wafer. After the device wafer has been thinned, the adhesive comprising phenoxy resin may be removed by laser debonding, wherein the device wafer is separated from the handling wafer.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: August 29, 2017
    Assignee: International Business Machines Corporation
    Inventors: Robert D. Allen, Paul S. Andry, Jeffrey D. Gelorme, Li-wen Hung, John U. Knickerbocker, Cornelia K. Tsang
  • Publication number: 20170144149
    Abstract: Techniques for use of wafer bonding techniques for sealing of microfluidic chips are provided. In one aspect, a wafer bonding sealing method includes the steps of: forming a first oxide layer coating surfaces of a first wafer, the first wafer having at least one fluidic chip; forming a second oxide layer on a second wafer; and bonding the first wafer to the second wafer via an oxide-to-oxide bond between the first oxide layer and the second oxide layer to form a bonded wafer pair, wherein the second oxide layer seals the at least one fluidic chip on the first wafer. The second wafer can be at least partially removed after performing the bonding, and fluidic ports may be formed in the second oxide layer. A fluidic chip device is also provided.
    Type: Application
    Filed: November 20, 2015
    Publication date: May 25, 2017
    Inventors: Joshua T. Smith, Cornelia K. Tsang, Chao Wang, Benjamin H. Wunsch
  • Patent number: 9648782
    Abstract: A package structure to implement two-phase cooling includes a chip stack disposed on a substrate, and a package lid that encloses the chip stack. The chip stack includes a plurality of conjoined chips, a central inlet manifold formed through a central region of the chip stack, and a peripheral outlet manifold. The central input manifold includes inlet nozzles to feed liquid coolant into flow cavities formed between adjacent conjoined chips. The peripheral outlet manifold outputs heated liquid and vapor from the flow cavities. The package lid includes a central coolant supply inlet aligned to the central inlet manifold, and a peripheral liquid-vapor outlet to output heated liquid and vapor that exits from the peripheral outlet manifold. Guiding walls may be included in the flow cavities to guide a flow of liquid and vapor, and the guiding walls can be arranged to form radial flow channels that are feed by different inlet nozzles of the central inlet manifold.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: May 9, 2017
    Assignee: International Business Machines Corporation
    Inventors: Thomas J. Brunschwiler, Evan G. Colgan, John U. Knickerbocker, Bruno Michael, Chin Lee Ong, Cornelia K. Tsang
  • Publication number: 20170125388
    Abstract: A package structure to implement two-phase cooling includes a chip stack disposed on a substrate, and a package lid that encloses the chip stack. The chip stack includes a plurality of conjoined chips, a central inlet manifold formed through a central region of the chip stack, and a peripheral outlet manifold. The central input manifold includes inlet nozzles to feed liquid coolant into flow cavities formed between adjacent conjoined chips. The peripheral outlet manifold outputs heated liquid and vapor from the flow cavities. The package lid includes a central coolant supply inlet aligned to the central inlet manifold, and a peripheral liquid-vapor outlet to output heated liquid and vapor that exits from the peripheral outlet manifold. Guiding walls may be included in the flow cavities to guide a flow of liquid and vapor, and the guiding walls can be arranged to form radial flow channels that are feed by different inlet nozzles of the central inlet manifold.
    Type: Application
    Filed: January 11, 2017
    Publication date: May 4, 2017
    Inventors: Thomas J. Brunschwiler, Evan G. Colgan, John U. Knickerbocker, Bruno Michael, Chin Lee Ong, Cornelia K. Tsang
  • Patent number: 9601364
    Abstract: A method for adhesive bonding in microelectronic device processing is provided that includes bonding a handling wafer to a front side of a device wafer with an adhesive comprising phenoxy resin; and thinning the device wafer from the backside of the device wafer while the device wafer is adhesively engaged to the handling wafer. After the device wafer has been thinned, the adhesive comprising phenoxy resin may be removed by laser debonding, wherein the device wafer is separated from the handling wafer.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: March 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert D. Allen, Paul S. Andry, Jeffrey D. Gelorme, Li-wen Hung, John U. Knickerbocker, Cornelia K. Tsang
  • Patent number: 9472789
    Abstract: A microsystem with an integrated energy source serves as a platform and ecosystem for a variety of microsystems for implanting into human tissue. The microsystem includes a flexible battery located in an enclosed void. The enclosed void is formed by joining a first dielectric element with a second dielectric element.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: October 18, 2016
    Assignee: International Business Machines Corporation
    Inventors: Paul S. Andry, Joana Sofia Branquinho Teresa Maria, Bing Dang, Michael A. Gaynes, John U. Knickerbocker, Eric P. Lewandowski, Cornelia K. Tsang, Bucknell C. Webb
  • Publication number: 20160204015
    Abstract: A method for adhesive bonding in microelectronic device processing is provided that includes bonding a handling wafer to a front side of a device wafer with an adhesive comprising phenoxy resin; and thinning the device wafer from the backside of the device wafer while the device wafer is adhesively engaged to the handling wafer. After the device wafer has been thinned, the adhesive comprising phenoxy resin may be removed by laser debonding, wherein the device wafer is separated from the handling wafer.
    Type: Application
    Filed: March 22, 2016
    Publication date: July 14, 2016
    Inventors: Robert D. Allen, Paul S. Andry, Jeffrey D. Gelorme, Li-wen Hung, John U. Knickerbocker, Cornelia K. Tsang
  • Publication number: 20160165758
    Abstract: A package structure to implement two-phase cooling includes a chip stack disposed on a substrate, and a package lid that encloses the chip stack. The chip stack includes a plurality of conjoined chips, a central inlet manifold formed through a central region of the chip stack, and a peripheral outlet manifold. The central input manifold includes inlet nozzles to feed liquid coolant into flow cavities formed between adjacent conjoined chips. The peripheral outlet manifold outputs heated liquid and vapor from the flow cavities. The package lid includes a central coolant supply inlet aligned to the central inlet manifold, and a peripheral liquid-vapor outlet to output heated liquid and vapor that exits from the peripheral outlet manifold. Guiding walls may be included in the flow cavities to guide a flow of liquid and vapor, and the guiding walls can be arranged to form radial flow channels that are feed by different inlet nozzles of the central inlet manifold.
    Type: Application
    Filed: February 11, 2016
    Publication date: June 9, 2016
    Inventors: Thomas J. Brunschwiler, Evan G. Colgan, John U. Knickerbocker, Bruno Michael, Chin Lee Ong, Cornelia K. Tsang
  • Patent number: 9362223
    Abstract: A method of forming an integrated circuit assembly includes forming an insulator layer on a preliminary semiconductor assembly. The preliminary semiconductor assembly includes a semiconductor substrate having a first side and a second side opposite the first side, a semiconductor circuitry layer formed on the first side of the semiconductor substrate, and a conductive via extending through the semiconductor substrate from the semiconductor circuitry layer to the second side. The insulator is formed on the second side and an end of the conductive via. The method includes forming a polymer layer on the insulator layer, removing a quantity of the polymer layer sufficient to expose the end of the conductive via through the insulator layer, and forming a conductive contact on the polymer layer and the end of the conductive via.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: June 7, 2016
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, HITACHI CHEMICIAL DUPONT MICROSYSTEMS, L.L.C.
    Inventors: Paul S. Andry, Sarah H. Knickerbocker, Ron R. Legario, Cornelia K. Tsang, Melvin P. Zussman
  • Patent number: 9355936
    Abstract: Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures of a product chip are formed using a first surface of a device substrate. A wiring layer of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate. The temporary handle wafer is then removed from the assembly.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: May 31, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Edward C. Cooney, III, James S. Dunn, Dale W. Martin, Charles S. Musante, BethAnn Rainey Lawrence, Leathen Shi, Edmund J. Sprogis, Cornelia K. Tsang
  • Publication number: 20160133498
    Abstract: A method for adhesive bonding in microelectronic device processing is provided that includes bonding a handling wafer to a front side of a device wafer with an adhesive comprising phenoxy resin; and thinning the device wafer from the backside of the device wafer while the device wafer is adhesively engaged to the handling wafer. After the device wafer has been thinned, the adhesive comprising phenoxy resin may be removed by laser debonding, wherein the device wafer is separated from the handling wafer.
    Type: Application
    Filed: November 7, 2014
    Publication date: May 12, 2016
    Inventors: Robert D. Allen, Paul S. Andry, Jeffrey D. Gelorme, Li-wen Hung, John U. Knickerbocker, Cornelia K. Tsang