Patents by Inventor Cornelia Kang-I Tsang
Cornelia Kang-I Tsang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160084876Abstract: A test probe structure having a planar surface and contact locations matched to test hardware is provided. The fabrication of the test probe structure addresses problems related to the possible deformation of base substrates during manufacture. Positional accuracy of contact locations and planarity of base substrates is achieved using dielectric layers, laser ablation, injection molded solder or redistribution layer wiring, and planarization techniques.Type: ApplicationFiled: September 24, 2014Publication date: March 24, 2016Inventors: Bing Dang, John U. Knickerbocker, Jae-Woong Nah, Robert E. Trzcinski, Cornelia Kang-I Tsang
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Patent number: 9269561Abstract: Methods are provided for handling a device wafer. For example, a method includes providing a stack structure having a device wafer, a handler wafer, and a bonding structure disposed between the device wafer and handler wafer, and irradiating the bonding structure with long-wavelength infrared energy to ablate the bonding structure.Type: GrantFiled: January 22, 2013Date of Patent: February 23, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Bing Dang, John U. Knickerbocker, Cornelia Kang-I Tsang
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Publication number: 20150340765Abstract: Package structures are provided for integrally packaging antennas with semiconductor RFIC (radio frequency integrated circuit) chips to form compact integrated radio/wireless communications systems that operate in the millimeter-wave and terahertz frequency ranges. For example, a package structure includes an RFIC chip, and an antenna package bonded to the RFIC chip. The antenna package includes a glass substrate, at least one planar antenna element formed on a first surface of the glass substrate, a ground plane formed on a second surface of the glass substrate, opposite the first surface, and an antenna feed line formed through the glass substrate and connected to the at least one planar antenna element. The antenna package is bonded to a surface of the RFIC chip using a layer of adhesive material.Type: ApplicationFiled: May 20, 2014Publication date: November 26, 2015Applicant: International Business Machines CorporationInventors: Bing Dang, Duixian Liu, Jean-Olivier Plouchart, Peter Jerome Sorce, Cornelia Kang-I Tsang
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Publication number: 20150035173Abstract: Methods are provided to form adhesive materials that are used to temporarily bond handler wafers to device wafers, and which enable mid-wavelength infrared laser ablation release techniques to release handler wafers from device wafers.Type: ApplicationFiled: March 27, 2014Publication date: February 5, 2015Applicant: International Business Machines CorporationInventors: Bing Dang, John U. Knickerbocker, Eric Peter Lewandowski, Cornelia Kang-I Tsang
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Publication number: 20150035554Abstract: Structures and methods are provided for temporarily bonding handler wafers to device wafers using bonding structures that include one or more releasable layers which are laser-ablatable using mid-wavelength infrared radiationType: ApplicationFiled: March 27, 2014Publication date: February 5, 2015Applicant: International Business Machines CorporationInventors: Bing Dang, John U. Knickerbocker, Cornelia Kang-I Tsang
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Patent number: 8806740Abstract: A silicon chicklet pedestal for use in a wafer-level test probe of a wafer is provided and includes a main body, first and second opposing faces, and an array of vias formed through the main body to extend between the first and second faces, through which pairs of leads, respectively associated with each via at the first and second faces, are electrically connectable to one another.Type: GrantFiled: April 28, 2011Date of Patent: August 19, 2014Assignee: International Business Machines CorporationInventors: S. Jay Chey, Timothy C. Krywanczyk, Mohammed S. Shaikh, Matthew T. Tiersch, Cornelia Kang-I Tsang
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Publication number: 20140144593Abstract: Structures and methods are provided for temporarily bonding handler wafers to device wafers using bonding structures that include one or more releasable layers that absorb long-wavelength infrared radiation to achieve wafer debonding by infrared radiation ablation.Type: ApplicationFiled: November 28, 2012Publication date: May 29, 2014Applicant: International Business Machiness CorporationInventors: Bing Dang, John U. Knickerbocker, Cornelia Kang-I Tsang
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Publication number: 20140147986Abstract: Methods are provided for handling a device wafer. For example, a method includes providing a stack structure having a device wafer, a handler wafer, and a bonding structure disposed between the device wafer and handler wafer, and irradiating the bonding structure with long-wavelength infrared energy to ablate the bonding structure.Type: ApplicationFiled: January 22, 2013Publication date: May 29, 2014Applicant: International Business Machines CorporationInventors: Bing Dang, John U. Knickerbocker, Cornelia Kang-I Tsang
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Patent number: 8735251Abstract: A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the substrate; (b) forming a silicon dioxide layer on sidewalls of the trench, the silicon dioxide layer not filling the trench; (c) filling remaining space in the trench with polysilicon; after (c), (d) fabricating at least a portion of a CMOS device in the substrate; (e) removing the polysilicon from the trench, the dielectric layer remaining on the sidewalls of the trench; (f) re-filling the trench with an electrically conductive core; and after (f), (g) forming one or more wiring layers over the top surface of the substrate, a wire of a wiring level of the one or more wiring levels closest to the substrate contacting a top surface of the conductive core.Type: GrantFiled: October 4, 2013Date of Patent: May 27, 2014Assignee: Ultratech, Inc.Inventors: Paul Stephen Andry, Edmund Juris Sprogis, Cornelia Kang-I Tsang
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Publication number: 20140094007Abstract: A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the substrate; (b) forming a silicon dioxide layer on sidewalls of the trench, the silicon dioxide layer not filling the trench; (c) filling remaining space in the trench with polysilicon; after (c), (d) fabricating at least a portion of a CMOS device in the substrate; (e) removing the polysilicon from the trench, the dielectric layer remaining on the sidewalls of the trench; (f) re-filling the trench with an electrically conductive core; and after (f), (g) forming one or more wiring layers over the top surface of the substrate, a wire of a wiring level of the one or more wiring levels closest to the substrate contacting a top surface of the conductive core.Type: ApplicationFiled: October 4, 2013Publication date: April 3, 2014Applicant: Ultratech, Inc.Inventors: Paul Stephen Andry, Edmund Juris Sprogis, Cornelia Kang-I Tsang
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Patent number: 8637937Abstract: A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the substrate; (b) forming a silicon dioxide layer on sidewalls of the trench, the silicon dioxide layer not filling the trench; (c) filling remaining space in the trench with polysilicon; after (c), (d) fabricating at least a portion of a CMOS device in the substrate; (e) removing the polysilicon from the trench, the dielectric layer remaining on the sidewalls of the trench; (f) re-filling the trench with an electrically conductive core; and after (f), (g) forming one or more wiring layers over the top surface of the substrate, a wire of a wiring level of the one or more wiring levels closest to the substrate contacting a top surface of the conductive core.Type: GrantFiled: February 2, 2012Date of Patent: January 28, 2014Assignee: Ultratech, Inc.Inventors: Paul Stephen Andry, Edmund Juris Sprogis, Cornelia Kang-I Tsang
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Patent number: 8595919Abstract: A silicon chicklet pedestal for use in a wafer-level test probe of a wafer is provided and includes a main body, first and second opposing faces, and an array of vias formed through the main body to extend between the first and second faces, through which pairs of leads, respectively associated with each via at the first and second faces, are electrically connectable to one another.Type: GrantFiled: April 28, 2011Date of Patent: December 3, 2013Assignee: International Business Machines CorporationInventors: S. Jay Chey, Timothy C. Krywanczyk, Mohammed S. Shaikh, Matthew T. Tiersch, Cornelia Kang-I Tsang
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Publication number: 20120132967Abstract: A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the substrate; (b) forming a silicon dioxide layer on sidewalls of the trench, the silicon dioxide layer not filling the trench; (c) filling remaining space in the trench with polysilicon; after (c), (d) fabricating at least a portion of a CMOS device in the substrate; (e) removing the polysilicon from the trench, the dielectric layer remaining on the sidewalls of the trench; (f) re-filling the trench with an electrically conductive core; and after (f), (g) forming one or more wiring layers over the top surface of the substrate, a wire of a wiring level of the one or more wiring levels closet to the substrate contacting a top surface of the conductive core.Type: ApplicationFiled: February 2, 2012Publication date: May 31, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul Stephen Andry, Edmund Juris Sprogis, Cornelia Kang-I Tsang
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Patent number: 8138036Abstract: A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the substrate; (b) forming a silicon dioxide layer on sidewalls of the trench, the silicon dioxide layer not filling the trench; (c) filling remaining space in the trench with polysilicon; after (c), (d) fabricating at least a portion of a CMOS device in the substrate; (e) removing the polysilicon from the trench, the dielectric layer remaining on the sidewalls of the trench; (f) re-filling the trench with an electrically conductive core; and after (f), (g) forming one or more wiring layers over the top surface of the substrate, a wire of a wiring level of the one or more wiring levels closet to the substrate contacting a top surface of the conductive core.Type: GrantFiled: August 8, 2008Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Paul Stephen Andry, Edmund Juris Sprogis, Cornelia Kang-I Tsang
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Patent number: 7987591Abstract: A silicon chicklet pedestal for use in a wafer-level test probe of a wafer is provided and includes a main body, first and second opposing faces, and an array of vias formed through the main body to extend between the first and second faces, through which pairs of leads, respectively associated with each via at the first and second faces, are electrically connectable to one another.Type: GrantFiled: August 13, 2009Date of Patent: August 2, 2011Assignee: International Business Machines CorporationInventors: S. Jay Chey, Timothy C. Krywanczyk, Mohammed S. Shaikh, Matthew T. Tiersch, Cornelia Kang-I Tsang
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Patent number: 7808798Abstract: An apparatus is described incorporating an interposer having a cavity for a portion of an antenna structure, having conductor through vias, a top Si part having interconnection wiring and having pads for electrically mounting an integrated circuit chip thereon, wherein the top Si part mates with the interposer electrically and mechanically. The interposer and top Si part may be scaled to provide an array of functional units. The invention overcomes the problem of combining a high efficient antenna with integrated circuit chips in a Si package with signal frequencies from 1 to 100 GHz and the problem of shielding components proximate to the antenna and reduces strain arising from mismatching of TCEs.Type: GrantFiled: April 4, 2008Date of Patent: October 5, 2010Assignee: International Business Machines CorporationInventors: John Michael Cotte, Brian Paul Gaucher, Janusz Grzyb, Nils Deneke Hoivik, Christopher Vincent Jahnes, John Ulrich Knickerbocker, Duixian Liu, John Harold Magerlein, Chirag Suryakant Patel, Ullrich R. Pfeiffer, Cornelia Kang-I Tsang
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Patent number: 7750459Abstract: An apparatus for an integrated module. A silicon carrier with through-silicon vias has a plurality of die connected to a top side of the silicon carrier. In addition, a substrate is connected to a bottom side of the silicon carrier. The substrate is coupled to the plurality of die via the through-silicon vias.Type: GrantFiled: February 1, 2008Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventors: Bing Dang, John Ulrich Knickerbocker, Cornelia Kang-I Tsang
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Patent number: 7741722Abstract: A through-wafer via structure and method for forming the same. The through-wafer via structure includes a wafer having an opening and a top wafer surface. The top wafer surface defines a first reference direction perpendicular to the top wafer surface. The through-wafer via structure further includes a through-wafer via in the opening. The through-wafer via has a shape of a rectangular plate. A height of the through-wafer via in the first reference direction essentially equals a thickness of the wafer in the first reference direction. A length of the through-wafer via in a second reference direction is at least ten times greater than a width of the through-wafer via in a third reference direction. The first, second, and third reference directions are perpendicular to each other.Type: GrantFiled: March 23, 2007Date of Patent: June 22, 2010Assignee: International Business Machines CorporationInventors: Paul Stephen Andry, Edmund Juris Sprogis, Kenneth Jay Stein, Timothy Dooling Sullivan, Cornelia Kang-I Tsang, Ping-Chuan Wang, Bucknell C. Webb
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Patent number: 7678696Abstract: A method of making a through wafer via. The method includes: forming a trench in a semiconductor substrate, the trench open to a top surface of the substrate; forming a polysilicon layer on sidewalls and a bottom of the trench; oxidizing the polysilicon layer to convert the polysilicon layer to a silicon oxide layer on the sidewalls and bottom of the trench, the silicon oxide layer not filling the trench; filling remaining space in the trench with an electrical conductor; and thinning the substrate from a bottom surface of the substrate and removing the silicon oxide layer from the bottom of the trench. The method may further include forming a metal layer on the silicon oxide layer before filling the trench.Type: GrantFiled: August 8, 2008Date of Patent: March 16, 2010Assignee: International Business Machines CorporationInventors: Paul Stephen Andry, Edmund Juris Sprogis, Cornelia Kang-I Tsang
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Publication number: 20100035430Abstract: A method of making a through wafer via. The method includes: forming a trench in a semiconductor substrate, the trench open to a top surface of the substrate; forming a polysilicon layer on sidewalls and a bottom of the trench; oxidizing the polysilicon layer to convert the polysilicon layer to a silicon oxide layer on the sidewalls and bottom of the trench, the silicon oxide layer not filling the trench; filling remaining space in the trench with an electrical conductor; and thinning the substrate from a bottom surface of the substrate and removing the silicon oxide layer from the bottom of the trench. The method may further include forming a metal layer on the silicon oxide layer before filling the trench.Type: ApplicationFiled: August 8, 2008Publication date: February 11, 2010Inventors: Paul Stephen Andry, Edmund Juris Sprogis, Cornelia Kang-I Tsang