Abstract: A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the substrate; (b) forming a silicon dioxide layer on sidewalls of the trench, the silicon dioxide layer not filling the trench; (c) filling remaining space in the trench with polysilicon; after (c), (d) fabricating at least a portion of a CMOS device in the substrate; (e) removing the polysilicon from the trench, the dielectric layer remaining on the sidewalls of the trench; (f) re-filling the trench with an electrically conductive core; and after (f), (g) forming one or more wiring layers over the top surface of the substrate, a wire of a wiring level of the one or more wiring levels closet to the substrate contacting a top surface of the conductive core.

Abstract: An apparatus for an integrated module. A silicon carrier with through-silicon vias has a plurality of die connected to a top side of the silicon carrier. In addition, a substrate is connected to a bottom side of the silicon carrier. The substrate is coupled to the plurality of die via the through-silicon vias.

Abstract: An apparatus is described incorporating an interposer having a cavity for a portion of an antenna structure, having conductor through vias, a top Si part having interconnection wiring and having pads for electrically mounting an integrated circuit chip thereon, wherein the top Si part mates with the interposer electrically and mechanically. The interposer and top Si part may be scaled to provide an array of functional units. The invention overcomes the problem of combining a high efficient antenna with integrated circuit chips in a Si package with signal frequencies from 1 to 100 GHz and the problem of shielding components proximate to the antenna and reduces strain arising from mismatching of TCEs.

Abstract: A through-wafer via structure and method for forming the same. The through-wafer via structure includes a wafer having an opening and a top wafer surface. The top wafer surface defines a first reference direction perpendicular to the top wafer surface. The through-wafer via structure further includes a through-wafer via in the opening. The through-wafer via has a shape of a rectangular plate. A height of the through-wafer via in the first reference direction essentially equals a thickness of the wafer in the first reference direction. A length of the through-wafer via in a second reference direction is at least ten times greater than a width of the through-wafer via in a third reference direction. The first, second, and third reference directions are perpendicular to each other.

Abstract: An apparatus is described incorporating an interposer having a cavity for a portion of an antenna structure, having conductor through vias, a top Si part having interconnection wiring and having pads for electrically mounting an integrated circuit chip thereon, wherein the top Si part mates with the interposer electrically and mechanically. The interposer and top Si part may be scaled to provide an array of functional units. The invention overcomes the problem of combining a high efficient antenna with integrated circuit chips in a Si package with signal frequencies from 1 to 100 GHz and the problem of shielding components proximate to the antenna and reduces strain arising from mismatching of TCEs.

Abstract: Flared and non-flared metallized deep vias having aspect ratios of about 2 or greater are provided. Blind vias have been fabricated in silicon substrates up to a depth of about 300 microns, and flared through vias have been fabricated up to about 750 microns, the approximate thickness of a silicon substrate wafer, enabling the formation of electrical connections at either or both ends of a via. In spite of the depth and high aspect ratios attainable, the etched vias are completely filled with plated copper conductor, completing the formation of deep vias and allowing fuller use of both sides of the substrate.