Patents by Inventor Cory E. Weber

Cory E. Weber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11011620
    Abstract: Techniques are disclosed for forming increasing channel region tensile strain in n-MOS devices. In some cases, increased channel region tensile strain can be achieved via S/D material engineering that deliberately introduces dislocations in one or both of the S/D regions to produce tensile strain in the adjacent channel region. In some such cases, the S/D material engineering to create desired dislocations may include using a lattice mismatched epitaxial S/D film adjacent to the channel region. Numerous material schemes for achieving multiple dislocations in one or both S/D regions will be apparent in light of this disclosure. In some cases, a cap layer can be formed on an S/D region to reduce contact resistance, such that the cap layer is an intervening layer between the S/D region and S/D contact. The cap layer includes different material than the underlying S/D region and/or a higher dopant concentration to reduce contact resistance.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: May 18, 2021
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Cory E. Weber, Anand S. Murthy, Karthik Jambunathan, Glenn A. Glass, Jiong Zhang, Ritesh Jhaveri, Szuya S. Liao
  • Patent number: 10991696
    Abstract: An integrated circuit structure is provided which comprises: a stack of source regions of a stack of transistors and a stack of drain regions of the stack of transistors; and a gate stack that forms gate regions for the stack of transistors, wherein the gate stack comprises traces of a first polymer of a block copolymer, the block copolymer comprising the first polymer and a second polymer.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: April 27, 2021
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Patrick Theofanis, Cory E. Weber, Stephen M. Cea, Rishabh Mehandru
  • Publication number: 20210074703
    Abstract: Semiconductor nanowire devices having (111)-plane channel sidewalls and methods of fabricating semiconductor nanowire devices having (111)-plane channel sidewalls are described. For example, an integrated circuit structure includes a first semiconductor device including a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires comprising a discrete channel region having <111> lateral sidewalls along a <110> carrier transport direction. The integrated circuit structure also includes a second semiconductor device including a semiconductor fin disposed above the substrate, the semiconductor fin having a channel region with a top and side surfaces, the channel region having <111> lateral sidewalls along a <110> carrier transport direction.
    Type: Application
    Filed: March 22, 2018
    Publication date: March 11, 2021
    Inventors: Cory E. WEBER, Haorld W. KENNEL, Willy RACHMADY, Gilbert DEWEY
  • Publication number: 20210043755
    Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.
    Type: Application
    Filed: October 26, 2020
    Publication date: February 11, 2021
    Inventors: Rishabh MEHANDRU, Patrick MORROW, Ranjith KUMAR, Cory E. WEBER, Seiyon KIM, Stephen M. CEA, Tahir GHANI
  • Publication number: 20210036137
    Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.
    Type: Application
    Filed: October 16, 2020
    Publication date: February 4, 2021
    Inventors: Stephen M. CEA, Cory E. WEBER, Patrick H. KEYS, Seiyon KIM, Michael G. HAVERTY, Sadasivan SHANKAR
  • Patent number: 10910405
    Abstract: Embodiments of the present invention are directed to formation of fins with different active channel heights in a tri-gate or a Fin-FET device. In an embodiment, at least two fins are formed on a front side of the substrate. A gate structure extends over a top surface and a pair of sidewalls of at least a portion of the fins. In an embodiment, the substrate is thinned to expose the bottom surface of the fins. Next, backside etching may be performed on each fin to form active channel regions. The fins may be recessed to different depths, forming active channel regions with differing heights.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Patrick Morrow, Stephen M. Cea, Rishabh Mehandru, Cory E. Weber
  • Publication number: 20200411690
    Abstract: An apparatus is provided which comprises: a first region over a substrate, wherein the first region comprises a first semiconductor material having a L-valley transport energy band structure, a second region in contact with the first region at a junction, wherein the second region comprises a second semiconductor material having a X-valley transport energy band structure, wherein a <111> crystal direction of one or more crystals of the first and second semiconductor materials are substantially orthogonal to the junction, and a metal adjacent to the second region, the metal conductively coupled to the first region through the junction. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: September 29, 2017
    Publication date: December 31, 2020
    Applicant: Intel Corporation
    Inventors: Dax M. Crum, Cory E. Weber, Rishabh Mehandru, Harold Kennel, Benjamin Chu-Kung
  • Patent number: 10847653
    Abstract: Semiconductor devices having metallic source and drain regions are described. For example, a semiconductor device includes a gate electrode stack disposed above a semiconducting channel region of a substrate. Metallic source and drain regions are disposed above the substrate, on either side of the semiconducting channel region. Each of the metallic source and drain regions has a profile. A first semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic source region, and conformal with the profile of the metallic source region. A second semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic drain region, and conformal with the profile of the metallic drain region.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Martin D. Giles, Annalisa Cappellani, Sanaz Gardner, Rafael Rios, Cory E. Weber, Aaron A. Budrevich
  • Patent number: 10847635
    Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Patrick Morrow, Ranjith Kumar, Cory E. Weber, Seiyon Kim, Stephen M. Cea, Tahir Ghani
  • Patent number: 10840366
    Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: November 17, 2020
    Assignee: Intel Corporation
    Inventors: Stephen M. Cea, Cory E. Weber, Patrick H. Keys, Seiyon Kim, Michael G. Haverty, Sadasivan Shankar
  • Publication number: 20200279910
    Abstract: Material systems for source region, drain region, and a semiconductor body of transistor devices in which the semiconductor body is electrically insulated from an underlying substrate are selected to reduce or eliminate a band to band tunneling (“BTBT”) effect between different energetic bands of the semiconductor body and one or both of the source region and the drain region. This can be accomplished by selecting a material for the semiconductor body with a band gap that is larger than a band gap for material(s) selected for the source region and/or drain region.
    Type: Application
    Filed: December 15, 2017
    Publication date: September 3, 2020
    Applicant: INTEL CORPORATION
    Inventors: Dipanjan Basu, Cory E. Weber, Justin R. Weber, Sean T. Ma, Harold W. Kennel, Seung Hoon Sung, Glenn A. Glass, Jack T. Kavalieros, Tahir Ghani
  • Publication number: 20200220024
    Abstract: A back-gated thin-film transistor (TFT) includes a gate electrode, a gate dielectric on the gate electrode, an active layer on the gate dielectric and having source and drain regions and a semiconductor region physically connecting the source and drain regions, a capping layer on the semiconductor region, and a charge trap layer on the capping layer. In an embodiment, a memory cell includes this back-gated TFT and a capacitor, the gate electrode being electrically connected to a wordline and the source region being electrically connected to a bitline, the capacitor having a first terminal electrically connected to the drain region, a second terminal, and a dielectric medium electrically separating the first and second terminals. In another embodiment, an embedded memory includes wordlines extending in a first direction, bitlines extending in a second direction crossing the first direction, and several such memory cells at crossing regions of the wordlines and bitlines.
    Type: Application
    Filed: September 29, 2017
    Publication date: July 9, 2020
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Van H. Le, Jack T. Kavalieros, Cory E. Weber, Sean T. Ma, Tahir Ghani, Shriram Shivaraman, Gilbert Dewey
  • Publication number: 20200176482
    Abstract: Embodiments of the present invention are directed to formation of fins with different active channel heights in a tri-gate or a Fin-FET device. In an embodiment, at least two fins are formed on a front side of the substrate. A gate structure extends over a top surface and a pair of sidewalls of at least a portion of the fins. In an embodiment, the substrate is thinned to expose the bottom surface of the fins. Next, backside etching may be performed on each fin to form active channel regions. The fins may be recessed to different depths, forming active channel regions with differing heights.
    Type: Application
    Filed: February 10, 2020
    Publication date: June 4, 2020
    Inventors: Aaron D. LILAK, Patrick MORROW, Stephen M. CEA, Rishabh MEHANDRU, Cory E. WEBER
  • Publication number: 20200144374
    Abstract: An electronic device comprises a first layer on a buffer layer on a substrate. A source/drain region is deposited on the buffer layer. The first layer comprises a first semiconductor. The source/drain region comprises a second semiconductor. The second semiconductor has a bandgap that is smaller than a bandgap of the first semiconductor. A gate electrode is deposited on the first layer.
    Type: Application
    Filed: June 30, 2017
    Publication date: May 7, 2020
    Inventors: Sean T. MA, Cory E. WEBER, Dipanjan BASU, Harold W. KENNEL, Willy RACHMADY, Gilbert DEWEY, Jack T. KAVALIEROS, Anand S. MURTHY, Tahir GHANI, Matthew V. METZ, Cheng-ying HUANG
  • Patent number: 10600810
    Abstract: Embodiments of the present invention are directed to formation of fins with different active channel heights in a tri-gate or a Fin-FET device. In an embodiment, at least two fins are formed on a front side of the substrate. A gate structure extends over a top surface and a pair of sidewalls of at least a portion of the fins. In an embodiment, the substrate is thinned to expose the bottom surface of the fins. Next, backside etching may be performed on each fin to form active channel regions. The fins may be recessed to different depths, forming active channel regions with differing heights.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: March 24, 2020
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Patrick Morrow, Stephen M. Cea, Rishabh Mehandru, Cory E. Weber
  • Publication number: 20200035818
    Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.
    Type: Application
    Filed: October 3, 2019
    Publication date: January 30, 2020
    Inventors: Stephen M. CEA, Cory E. WEBER, Patrick H. KEYS, Seiyon KIM, Michael G. HAVERTY, Sadasivan SHANKAR
  • Publication number: 20200013861
    Abstract: Substrates, assemblies, and techniques for a backend transistor, where the backend transistor includes a gate, a semiconductor oxide, a source metal and a drain metal, and an insulator between the source metal and the gate and between the drain metal and the gate. The insulator can allow for tunneling between the source metal and/or the drain metal and the semiconductor oxide.
    Type: Application
    Filed: March 31, 2017
    Publication date: January 9, 2020
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Van H. Le, Gilbert W. Dewey, Shriram Shivaraman, Tahir Ghani, Jack T. Kavalieros, Cory E. Weber
  • Patent number: 10497781
    Abstract: Methods for doping a sub-fin region of a semiconductor structure include providing a semiconductor structure that comprises a substrate and a plurality of fins formed on the substrate, the plurality of fins having sub-fin regions adjacent to the substrate; removing the substrate to expose a portion of the sub-fin regions of the plurality of fins, and implanting a dopant material into the exposed portion of the sub-fin region. The method may also include performing an annealing process after the implantation such that the dopant becomes electrically active. The method may also include patterning the backside of the semiconductor structure. Devices constructed using the disclosed methods are also provided, and other embodiments are discussed.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: December 3, 2019
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Stephen M. Cea, Rishabh Mehandru, Cory E. Weber
  • Patent number: 10483385
    Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: November 19, 2019
    Assignee: Intel Corporation
    Inventors: Stephen M. Cea, Cory E. Weber, Patrick H. Keys, Seiyon Kim, Michael G. Haverty, Sadasivan Shankar
  • Publication number: 20190341384
    Abstract: An integrated circuit structure is provided which comprises: a stack of source regions of a stack of transistors and a stack of drain regions of the stack of transistors; and a gate stack that forms gate regions for the stack of transistors, wherein the gate stack comprises traces of a first polymer of a block copolymer, the block copolymer comprising the first polymer and a second polymer.
    Type: Application
    Filed: March 15, 2017
    Publication date: November 7, 2019
    Applicant: Intel Corporation
    Inventors: Aaron D. Lilak, Patrick Theofanis, Cory E. Weber, Stephen M. Cea, Rishabh Mehandru