Patents by Inventor Cory E. Weber
Cory E. Weber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10840366Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.Type: GrantFiled: October 3, 2019Date of Patent: November 17, 2020Assignee: Intel CorporationInventors: Stephen M. Cea, Cory E. Weber, Patrick H. Keys, Seiyon Kim, Michael G. Haverty, Sadasivan Shankar
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Publication number: 20200279910Abstract: Material systems for source region, drain region, and a semiconductor body of transistor devices in which the semiconductor body is electrically insulated from an underlying substrate are selected to reduce or eliminate a band to band tunneling (“BTBT”) effect between different energetic bands of the semiconductor body and one or both of the source region and the drain region. This can be accomplished by selecting a material for the semiconductor body with a band gap that is larger than a band gap for material(s) selected for the source region and/or drain region.Type: ApplicationFiled: December 15, 2017Publication date: September 3, 2020Applicant: INTEL CORPORATIONInventors: Dipanjan Basu, Cory E. Weber, Justin R. Weber, Sean T. Ma, Harold W. Kennel, Seung Hoon Sung, Glenn A. Glass, Jack T. Kavalieros, Tahir Ghani
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Publication number: 20200220024Abstract: A back-gated thin-film transistor (TFT) includes a gate electrode, a gate dielectric on the gate electrode, an active layer on the gate dielectric and having source and drain regions and a semiconductor region physically connecting the source and drain regions, a capping layer on the semiconductor region, and a charge trap layer on the capping layer. In an embodiment, a memory cell includes this back-gated TFT and a capacitor, the gate electrode being electrically connected to a wordline and the source region being electrically connected to a bitline, the capacitor having a first terminal electrically connected to the drain region, a second terminal, and a dielectric medium electrically separating the first and second terminals. In another embodiment, an embedded memory includes wordlines extending in a first direction, bitlines extending in a second direction crossing the first direction, and several such memory cells at crossing regions of the wordlines and bitlines.Type: ApplicationFiled: September 29, 2017Publication date: July 9, 2020Applicant: Intel CorporationInventors: Abhishek A. Sharma, Van H. Le, Jack T. Kavalieros, Cory E. Weber, Sean T. Ma, Tahir Ghani, Shriram Shivaraman, Gilbert Dewey
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Publication number: 20200176482Abstract: Embodiments of the present invention are directed to formation of fins with different active channel heights in a tri-gate or a Fin-FET device. In an embodiment, at least two fins are formed on a front side of the substrate. A gate structure extends over a top surface and a pair of sidewalls of at least a portion of the fins. In an embodiment, the substrate is thinned to expose the bottom surface of the fins. Next, backside etching may be performed on each fin to form active channel regions. The fins may be recessed to different depths, forming active channel regions with differing heights.Type: ApplicationFiled: February 10, 2020Publication date: June 4, 2020Inventors: Aaron D. LILAK, Patrick MORROW, Stephen M. CEA, Rishabh MEHANDRU, Cory E. WEBER
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Publication number: 20200144374Abstract: An electronic device comprises a first layer on a buffer layer on a substrate. A source/drain region is deposited on the buffer layer. The first layer comprises a first semiconductor. The source/drain region comprises a second semiconductor. The second semiconductor has a bandgap that is smaller than a bandgap of the first semiconductor. A gate electrode is deposited on the first layer.Type: ApplicationFiled: June 30, 2017Publication date: May 7, 2020Inventors: Sean T. MA, Cory E. WEBER, Dipanjan BASU, Harold W. KENNEL, Willy RACHMADY, Gilbert DEWEY, Jack T. KAVALIEROS, Anand S. MURTHY, Tahir GHANI, Matthew V. METZ, Cheng-ying HUANG
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Patent number: 10600810Abstract: Embodiments of the present invention are directed to formation of fins with different active channel heights in a tri-gate or a Fin-FET device. In an embodiment, at least two fins are formed on a front side of the substrate. A gate structure extends over a top surface and a pair of sidewalls of at least a portion of the fins. In an embodiment, the substrate is thinned to expose the bottom surface of the fins. Next, backside etching may be performed on each fin to form active channel regions. The fins may be recessed to different depths, forming active channel regions with differing heights.Type: GrantFiled: September 25, 2015Date of Patent: March 24, 2020Assignee: Intel CorporationInventors: Aaron D. Lilak, Patrick Morrow, Stephen M. Cea, Rishabh Mehandru, Cory E. Weber
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Publication number: 20200035818Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.Type: ApplicationFiled: October 3, 2019Publication date: January 30, 2020Inventors: Stephen M. CEA, Cory E. WEBER, Patrick H. KEYS, Seiyon KIM, Michael G. HAVERTY, Sadasivan SHANKAR
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Publication number: 20200013861Abstract: Substrates, assemblies, and techniques for a backend transistor, where the backend transistor includes a gate, a semiconductor oxide, a source metal and a drain metal, and an insulator between the source metal and the gate and between the drain metal and the gate. The insulator can allow for tunneling between the source metal and/or the drain metal and the semiconductor oxide.Type: ApplicationFiled: March 31, 2017Publication date: January 9, 2020Applicant: Intel CorporationInventors: Abhishek A. Sharma, Van H. Le, Gilbert W. Dewey, Shriram Shivaraman, Tahir Ghani, Jack T. Kavalieros, Cory E. Weber
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Patent number: 10497781Abstract: Methods for doping a sub-fin region of a semiconductor structure include providing a semiconductor structure that comprises a substrate and a plurality of fins formed on the substrate, the plurality of fins having sub-fin regions adjacent to the substrate; removing the substrate to expose a portion of the sub-fin regions of the plurality of fins, and implanting a dopant material into the exposed portion of the sub-fin region. The method may also include performing an annealing process after the implantation such that the dopant becomes electrically active. The method may also include patterning the backside of the semiconductor structure. Devices constructed using the disclosed methods are also provided, and other embodiments are discussed.Type: GrantFiled: December 23, 2015Date of Patent: December 3, 2019Assignee: Intel CorporationInventors: Aaron D. Lilak, Stephen M. Cea, Rishabh Mehandru, Cory E. Weber
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Patent number: 10483385Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.Type: GrantFiled: December 23, 2011Date of Patent: November 19, 2019Assignee: Intel CorporationInventors: Stephen M. Cea, Cory E. Weber, Patrick H. Keys, Seiyon Kim, Michael G. Haverty, Sadasivan Shankar
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Publication number: 20190341384Abstract: An integrated circuit structure is provided which comprises: a stack of source regions of a stack of transistors and a stack of drain regions of the stack of transistors; and a gate stack that forms gate regions for the stack of transistors, wherein the gate stack comprises traces of a first polymer of a block copolymer, the block copolymer comprising the first polymer and a second polymer.Type: ApplicationFiled: March 15, 2017Publication date: November 7, 2019Applicant: Intel CorporationInventors: Aaron D. Lilak, Patrick Theofanis, Cory E. Weber, Stephen M. Cea, Rishabh Mehandru
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Patent number: 10411090Abstract: Hybrid trigate and nanowire CMOS device architecture, and methods of fabricating hybrid trigate and nanowire CMOS device architecture, are described. For example, a semiconductor structure includes a semiconductor device of a first conductivity type having a plurality of vertically stacked nanowires disposed above a substrate. The semiconductor structure also includes a semiconductor device of a second conductivity type opposite the first conductivity type, the second semiconductor device having a semiconductor fin disposed above the substrate.Type: GrantFiled: September 24, 2015Date of Patent: September 10, 2019Assignee: Intel CorporationInventors: Cory E. Weber, Rishabh Mehandru, Stephen M. Cea
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Publication number: 20190267448Abstract: Methods and structures formed thereby are described relating to the doping non-planar fin structures. An embodiment of a structure includes a substrate, wherein the substrate comprises silicon, a fin on the substrate comprising a first portion and a second portion; and a dopant species, wherein the first portion comprises a first dopant species concentration, and the second portion comprises a second dopant species concentration, wherein the first dopant species concentration is substantially less than the second dopant species concentration.Type: ApplicationFiled: May 14, 2019Publication date: August 29, 2019Applicant: Intel CorporationInventors: Cory E. Weber, Aaron D. Lilak, Szuya S. Liao, Aaron A. Budrevich
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Publication number: 20190252525Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.Type: ApplicationFiled: April 26, 2019Publication date: August 15, 2019Inventors: Rishabh MEHANDRU, Patrick MORROW, Ranjith KUMAR, Cory E. WEBER, Seiyon KIM, Stephen M. CEA, Tahir GHANI
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Publication number: 20190207015Abstract: Techniques are disclosed for forming increasing channel region tensile strain in n-MOS devices. In some cases, increased channel region tensile strain can be achieved via S/D material engineering that deliberately introduces dislocations in one or both of the S/D regions to produce tensile strain in the adjacent channel region. In some such cases, the S/D material engineering to create desired dislocations may include using a lattice mismatched epitaxial S/D film adjacent to the channel region. Numerous material schemes for achieving multiple dislocations in one or both S/D regions will be apparent in light of this disclosure. In some cases, a cap layer can be formed on an S/D region to reduce contact resistance, such that the cap layer is an intervening layer between the S/D region and S/D contact. The cap layer includes different material than the underlying S/D region and/or a higher dopant concentration to reduce contact resistance.Type: ApplicationFiled: September 27, 2016Publication date: July 4, 2019Applicant: INTEL CORPORATIONInventors: RISHABH MEHANDRU, CORY E. WEBER, ANAND S. MURTHY, KARTHIK JAMBUNATHAN, GLENN A. GLASS, JIONG ZHANG, RITESH JHAVERI, SZUYA S. LIAO
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Patent number: 10304946Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.Type: GrantFiled: June 17, 2015Date of Patent: May 28, 2019Assignee: Intel CorporationInventors: Rishabh Mehandru, Patrick Morrow, Ranjith Kumar, Cory E. Weber, Seiyon Kim, Stephen M. Cea, Tahir Ghani
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Publication number: 20190027503Abstract: Embodiments of the present invention are directed to formation of fins with different active channel heights in a tri-gate or a Fin-FET device. In an embodiment, at least two fins are formed on a front side of the substrate. A gate structure extends over a top surface and a pair of sidewalls of at least a portion of the fins. In an embodiment, the substrate is thinned to expose the bottom surface of the fins. Next, backside etching may be performed on each fin to form active channel regions. The fins may be recessed to different depths, forming active channel regions with differing heights.Type: ApplicationFiled: September 25, 2015Publication date: January 24, 2019Inventors: Aaron D. LILAK, Patrick MORROW, Stephen M. CEA, Rishabh MEHANDRU, Cory E. WEBER
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Patent number: 10084087Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.Type: GrantFiled: April 17, 2017Date of Patent: September 25, 2018Assignee: Intel CorporationInventors: Cory E. Weber, Mark Y. Liu, Anand S. Murthy, Hemant V. Deshpande, Daniel B. Aubertine
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Publication number: 20180254320Abstract: Methods and structures formed thereby are described relating to the doping non-planar fin structures. An embodiment of a structure includes a substrate, wherein the substrate comprises silicon, a fin on the substrate comprising a first portion and a second portion; and a dopant species, wherein the first portion comprises a first dopant species concentration, and the second portion comprises a second dopant species concentration, wherein the first dopant species concentration is substantially less than the second dopant species concentration.Type: ApplicationFiled: September 25, 2015Publication date: September 6, 2018Applicant: Intel CorporationInventors: Cory E. Weber, Aaron D. Lilak, Szuya S. Liao, Aaron A. Budrevich
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Publication number: 20180248005Abstract: Methods for doping a sub-fin region of a semiconductor structure include providing a semiconductor structure that comprises a substrate and a plurality of fins formed on the substrate, the plurality of fins having sub-fin regions adjacent to the substrate; removing the substrate to expose a portion of the sub-fin regions of the plurality of fins, and implanting a dopant material into the exposed portion of the sub-fin region. The method may also include performing an annealing process after the implantation such that the dopant becomes electrically active. The method may also include patterning the backside of the semiconductor structure. Devices constructed using the disclosed methods are also provided, and other embodiments are discussed.Type: ApplicationFiled: December 23, 2015Publication date: August 30, 2018Inventors: Aaron D. LILAK, Stephen M. CEA, Rishabh MEHANDRU, Cory E. WEBER