Patents by Inventor Cory Wajda
Cory Wajda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240153781Abstract: Embodiments of methods are provided for thermal dry etching of a ruthenium (Ru) metal layer. In the disclosed embodiments, a substrate containing a Ru metal layer formed thereon is exposed to a gas pulse sequence, while the substrate is held at a relatively high substrate temperature (e.g., a temperature greater than or equal to about 160° C.), to provide thermal etching of the Ru metal layer. As described further herein, the gas pulse sequence may generally include a plurality of gas pulses, which are supplied to the substrate sequentially with substantially no overlap between gas pulses. The gas pulses supplied to the substrate form: (i) volatile reaction products that are vaporized from the Ru surface, and (ii) non-volatile oxide surface layers that are removed from the Ru surface by the next gas pulse, resulting in atomic layer etching (ALE) of the Ru metal layer.Type: ApplicationFiled: October 31, 2023Publication date: May 9, 2024Inventors: Hisashi Higuchi, Kai-Hung Yu, Cory Wajda, Gyanaranjan Pattanaik, Kandabara Tapily, Gerrit Leusink, Robert Clark
-
Publication number: 20230274932Abstract: A method for processing a substrate includes treating the substrate with a small molecular inhibitor (SMI), the substrate including a recess formed in a dielectric layer and a first metal layer in the recess, the SMI covering a surface of the first metal layer. The method further includes, after treating the substrate with the SMI, treating the substrate with a large molecular inhibitor (LMI), the LMI covering sidewalls of the dielectric layer in the recess. The method further includes heating the substrate to remove the SMI from the first metal layer and to expose the first metal layer in the recess, where the LMI remains on the sidewalls after removing the SMI from the first metal layer. The method further includes depositing a second metal over the first metal layer in the recess, where the LMI covering the sidewalls prevents deposition of the second metal on the dielectric layer.Type: ApplicationFiled: January 18, 2023Publication date: August 31, 2023Inventors: Kai-Hung Yu, Robert D. Clark, Ryota Yonezawa, Hiroaki Niimi, Hidenao Suzuki, Kandabara Tapily, Takahiro Miyahara, Cory Wajda
-
Patent number: 11700778Abstract: A method of controlling the forming voltage of a dielectric film in a resistive random access memory (ReRAM) device. The method includes depositing a dielectric film contains intrinsic defects on a substrate, forming a plasma-excited treatment gas containing H2 gas, and exposing the dielectric film to the plasma-excited treatment gas to create additional defects in the dielectric film without substantially changing a physical thickness of the dielectric film, where the additional defects lower the forming voltage needed for generating an electrically conducting filament across the dielectric film. The dielectric film can include a metal oxide film and the plasma-excited treatment gas may be formed using a microwave plasma source.Type: GrantFiled: April 9, 2021Date of Patent: July 11, 2023Assignee: Tokyo Electron LimitedInventors: Steven Consiglio, Cory Wajda, Kandabara Tapily, Takaaki Tsunomura, Takashi Ando, Paul C. Jamison, Eduard A. Cartier, Vijay Narayanan, Marinus J. P. Hopstaken
-
Patent number: 11621190Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.Type: GrantFiled: May 28, 2021Date of Patent: April 4, 2023Assignee: Tokyo Electron LimitedInventors: Kai-Hung Yu, David O'Meara, Nicholas Joy, Gyanaranjan Pattanaik, Robert Clark, Kandabara Tapily, Takahiro Hakamata, Cory Wajda, Gerrit Leusink
-
Publication number: 20220301930Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, forming a nucleation enhancement layer on a sidewall of the first layer in the recessed feature and depositing a metal layer in the recessed feature by vapor phase deposition, where the metal layer is deposited on the second layer and on the nucleation enhancement layer. An initial metal layer may be selectively formed on the second layer in the recessed feature before forming the nucleation enhancement layer.Type: ApplicationFiled: March 7, 2022Publication date: September 22, 2022Inventors: Kai-Hung Yu, Shihsheng Chang, Ying Trickett, Eric Chih-Fang Liu, Yun Han, Henan Zhang, Cory Wajda, Robert D. Clark, Gerrit J. Leusink, Gyanaranjan Pattanaik, Hiroaki Niimi
-
Publication number: 20220139776Abstract: A method for filling recessed features with a low-resistivity metal includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, and depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature. The method further includes removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature, where the removing includes exposing the patterned substrate to an etching gas containing ozone.Type: ApplicationFiled: October 21, 2021Publication date: May 5, 2022Inventors: Kai-Hung Yu, David L. O'Meara, Hisashi Higuchi, Hirokazu Aizawa, Omid Zandi, Cory Wajda, Gerrit J. Leusink
-
Publication number: 20210287936Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.Type: ApplicationFiled: May 28, 2021Publication date: September 16, 2021Inventors: Kai-Hung Yu, David O'Meara, Nicholas Joy, Gyanaranjan Pattanaik, Robert Clark, Kandabara Tapily, Takahiro Hakamata, Cory Wajda, Gerrit Leusink
-
Publication number: 20210234096Abstract: A method of controlling the forming voltage of a dielectric film in a resistive random access memory (ReRAM) device. The method includes depositing a dielectric film contains intrinsic defects on a substrate, forming a plasma-excited treatment gas containing H2 gas, and exposing the dielectric film to the plasma-excited treatment gas to create additional defects in the dielectric film without substantially changing a physical thickness of the dielectric film, where the additional defects lower the forming voltage needed for generating an electrically conducting filament across the dielectric film. The dielectric film can include a metal oxide film and the plasma-excited treatment gas may be formed using a microwave plasma source.Type: ApplicationFiled: April 9, 2021Publication date: July 29, 2021Inventors: Steven Consiglio, Cory Wajda, Kandabara Tapily, Takaaki Tsunomura, Takashi Ando, Paul C. Jamison, Eduard A. Cartier, Vijay Narayanan, Marinus J.P. Hopstaken
-
Patent number: 11024535Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.Type: GrantFiled: October 10, 2019Date of Patent: June 1, 2021Assignee: Tokyo Electron LimitedInventors: Kai-Hung Yu, David O'Meara, Nicholas Joy, Gyanaranjan Pattanaik, Robert Clark, Kandabara Tapily, Takahiro Hakamata, Cory Wajda, Gerrit Leusink
-
Patent number: 10991881Abstract: A method of controlling the forming voltage of a dielectric film in a resistive random access memory (ReRAM) device. The method includes depositing a dielectric film contains intrinsic defects on a substrate, forming a plasma-excited treatment gas containing H2 gas, and exposing the dielectric film to the plasma-excited treatment gas to create additional defects in the dielectric film without substantially changing a physical thickness of the dielectric film, where the additional defects lower the forming voltage needed for generating an electrically conducting filament across the dielectric film. The dielectric film can include a metal oxide film and the plasma-excited treatment gas may be formed using a microwave plasma source.Type: GrantFiled: May 31, 2019Date of Patent: April 27, 2021Assignee: Tokyo Electron LimitedInventors: Steven Consiglio, Cory Wajda, Kandabara Tapily, Takaaki Tsunomura, Takashi Ando, Paul C. Jamison, Eduard A. Cartier, Vijay Narayanan, Marinus J. P. Hopstaken
-
Patent number: 10950460Abstract: A process is provided in which etched layer(s) are protected from residues or defects caused by or resulting from exposure to atmospheric conditions. Protection is provided through the formation of an encapsulation layer post etch. In one embodiment, the encapsulation is provided by a thin layer formed in an atomic layer deposition (ALD) process. The thin layer prevents the etched layer(s) from exposure to air. This encapsulation process may take place after the etch process thus allowing for substrates to be subsequently exposed to atmospheric conditions with little or no queue time constraints being needed for staging subsequent wet clean processing steps. In one embodiment, the encapsulation process may be performed with no vacuum break between the etch process and the encapsulation process. In one embodiment, the encapsulation film is compatible with subsequent wet process steps and can be removed during this wet process steps without adverse effects.Type: GrantFiled: August 6, 2019Date of Patent: March 16, 2021Assignee: TOKYO ELECTRON LIMITEDInventors: Angelique Raley, Andrew Metz, Cory Wajda, Junling Sun
-
Publication number: 20200381624Abstract: A method of controlling the forming voltage of a dielectric film in a resistive random access memory (ReRAM) device. The method includes depositing a dielectric film contains intrinsic defects on a substrate, forming a plasma-excited treatment gas containing H2 gas, and exposing the dielectric film to the plasma-excited treatment gas to create additional defects in the dielectric film without substantially changing a physical thickness of the dielectric film, where the additional defects lower the forming voltage needed for generating an electrically conducting filament across the dielectric film. The dielectric film can include a metal oxide film and the plasma-excited treatment gas may be formed using a microwave plasma source.Type: ApplicationFiled: May 31, 2019Publication date: December 3, 2020Inventors: Steven Consiglio, Cory Wajda, Kandabara Tapily, Takaaki Tsunomura, Takashi Ando, Paul C. Jamison, Eduard A. Cartier, Vijay Narayanan, Marinus J.P. Hopstaken
-
Patent number: 10700009Abstract: A method is provided for void-free Ru metal filling of features in a substrate. The method includes providing a substrate containing features, depositing a Ru metal layer in the features, removing the Ru metal layer from a field area around an opening of the features, and depositing additional Ru metal in the features, where the additional Ru metal is deposited in the features at a higher rate than on the field area. According to one embodiment, the additional Ru metal is deposited until the features are fully filled with Ru metal.Type: GrantFiled: October 1, 2018Date of Patent: June 30, 2020Assignee: Tokyo Electron LimitedInventors: Kai-Hung Yu, Nicholas Joy, Eric Chih Fang Liu, David L. O'Meara, David Rosenthal, Masanobu Igeta, Cory Wajda, Gerrit J. Leusink
-
Publication number: 20200118871Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.Type: ApplicationFiled: October 10, 2019Publication date: April 16, 2020Inventors: Kai-Hung Yu, David O'Meara, Nicholas Joy, Gyanaranjan Pattanaik, Robert Clark, Kandabara Tapily, Takahiro Hakamata, Cory Wajda, Gerrit Leusink
-
Publication number: 20200051832Abstract: A process is provided in which etched layer(s) are protected from residues or defects caused by or resulting from exposure to atmospheric conditions. Protection is provided through the formation of an encapsulation layer post etch. In one embodiment, the encapsulation is provided by a thin layer formed in an atomic layer deposition (ALD) process. The thin layer prevents the etched layer(s) from exposure to air. This encapsulation process may take place after the etch process thus allowing for substrates to be subsequently exposed to atmospheric conditions with little or no queue time constraints being needed for staging subsequent wet clean processing steps. In one embodiment, the encapsulation process may be performed with no vacuum break between the etch process and the encapsulation process. In one embodiment, the encapsulation film is compatible with subsequent wet process steps and can be removed during this wet process steps without adverse effects.Type: ApplicationFiled: August 6, 2019Publication date: February 13, 2020Inventors: Angelique Raley, Andrew Metz, Cory Wajda, Junling Sun
-
Publication number: 20190103363Abstract: A method is provided for void-free Ru metal filling of features in a substrate. The method includes providing a substrate containing features, depositing a Ru metal layer in the features, removing the Ru metal layer from a field area around an opening of the features, and depositing additional Ru metal in the features, where the additional Ru metal is deposited in the features at a higher rate than on the field area. According to one embodiment, the additional Ru metal is deposited until the features are fully filled with Ru metal.Type: ApplicationFiled: October 1, 2018Publication date: April 4, 2019Inventors: Kai-Hung Yu, Nicholas Joy, Eric Chih Fang Liu, David L. O'Meara, David Rosenthal, Masanobu Igeta, Cory Wajda, Gerrit J. Leusink
-
Patent number: 10157784Abstract: Methods for integration of conformal barrier layers and Ru metal liners with Cu metallization in semiconductor manufacturing are described in several embodiments. According to one embodiment, the method includes providing a substrate containing a recessed feature, depositing a barrier layer in the recessed feature, depositing a Ru metal liner on the barrier layer, and exposing the substrate to an oxidation source gas to oxidize the barrier layer through the Ru metal liner. The method further includes filling the recessed feature with CuMn metal using an ionized physical vapor deposition (IPVD) process, heat-treating the substrate to diffuse Mn from the CuMn metal to the oxidized barrier layer, and reacting the diffused Mn with the oxidized barrier layer to form a Mn-containing diffusion barrier.Type: GrantFiled: February 9, 2017Date of Patent: December 18, 2018Assignee: Tokyo Electron LimitedInventors: Kai-Hung Yu, Manabu Oie, Kaoru Maekawa, Cory Wajda, Gerrit J. Leusink, Yuuki Kikuchi, Hiroaki Kawasaki, Hiroyuki Nagai
-
Patent number: 10068764Abstract: Embodiments of the invention provide methods for selective film deposition using a surface pretreatment. According to one embodiment, the method includes providing a substrate containing a dielectric layer and a metal layer, exposing the substrate to a reactant gas containing a molecule that forms self-assembled monolayers (SAMs) on the substrate, and thereafter, selectively depositing a metal oxide film on a surface of the dielectric layer relative to a surface of the metal layer by exposing the substrate to a deposition gas.Type: GrantFiled: September 12, 2017Date of Patent: September 4, 2018Assignee: Tokyo Electron LimitedInventors: Kandabara N. Tapily, Gerrit J. Leusink, Cory Wajda, Hoyoung Kang
-
Patent number: 10056328Abstract: A method is provided for at least partially filling a feature in a substrate. The method includes providing a substrate containing a feature, depositing a ruthenium (Ru) metal layer to at least partially fill the feature, and heat-treating the substrate to reflow the Ru metal layer in the feature.Type: GrantFiled: July 17, 2017Date of Patent: August 21, 2018Assignee: Tokyo Electron LimitedInventors: Kai-Hung Yu, Gerrit J. Leusink, Cory Wajda, Tadahiro Ishizaka, Takahiro Hakamata
-
Patent number: 10008564Abstract: Embodiments of the invention describe a method of corner rounding and trimming of nanowires used in semiconductor devices. According to one embodiment, the method includes providing in a process chamber a plurality of nanowires separated from each other by a void, where the plurality of nanowires have a height and at least substantially right angle corners, forming an oxidized surface layer on the plurality of nanowires using an oxidizing microwave plasma, removing the oxidized surface layer to trim the height and round the corners of the plurality of nanowires, and repeating the forming and removing at least once until the plurality of nanowires have a desired trimmed height and rounded corners.Type: GrantFiled: November 3, 2016Date of Patent: June 26, 2018Assignee: Tokyo Electron LimitedInventors: Kandabara N. Tapily, Ying Trickett, Chihiro Tamura, Cory Wajda, Gerrit J. Leusink, Kaoru Maekawa